The move to 7nm pushes design to new limits

2 mins read

While chipmakers are keen to move to the 7nm node, the use of ‘tricks’ to extend the life of optical lithography, amidst a continuing wait for EUV, is piling up the design challenges.

“In the last five to six years, we have gone through six to seven nodes, starting with variants of 28nm,” said Balaji Velikandanathan, quality engineer at Qualcomm, in a panel session at June’s Design Automation Conference. “We are talking about [moving from] inception to tapeout in nine months and [introducing] a new process node every year.”

Qualcomm wants to move to 7nm to push frequency to 3GHz and reduce power by 30%, compared to the 10nm Snapdragon 835 used in phones such as the HTC U11.

But the need to use self-aligned double patterning (SADP) to form the densest metal interconnect layers brings with it complex new design rules, as well as much higher resistance in the wiring itself. With SADP, metal lines have to run parallel to each other on each layer. Any connection that includes one or more turns needs to use at least two metal layers, incurring the resistance cost of vias, as well as the very thin metal wires.

To work around high resistance in signal lines that need high switching speeds, foundries have adopted via pillars or via ladders and encourage the use of the coarser metal on upper layers for high-speed signals that would be prone to electromigration if routed on the finer wiring layers. The pillars use two vias in parallel to move up each layer, which reduces overall resistance.

“The via pillar doesn’t come for free,” said Velikandanathan. “It uses additional routing resources and places additional challenges on the router.”

Foundries such as GlobalFoundries (GF) and TSMC have involved designers in the creation of their 7nm processes in order to work out how to make designs economic and to claw back drops in silicon utilisation incurred by structures such as via pillars. “There is no free lunch,” said GF’s design-enablement fellow Greg Northrop. “You have to make compromises but, ultimately, everybody’s real interest is making sure the final cost is minimised. A major impact is that we end up with a significantly ‘scrunched’ standard cell and this will impact the way in which libraries interact with the router.”

One of the biggest problems for design with standard cells is providing access points for the router to the pins of each gate. This problem is exacerbated by rules governing SADP that make small jogs in local routing extremely expensive. Synopsys, for example, found in early work with GF that it often makes more sense to move cells around so an interconnect can use a single straight line.

A future shift to EUV patterning for the lowest metal layers may relax the rules for designers, making it easier to hit density and speed targets. Samsung said at the VLSI Technology Symposium that use of EUV in critical layers reduced routing congestion and improved speed by removing the excess parasitic capacitance of the dummy metal lines needed by SADP-based processes.

Willy Chen, deputy director of TSMC’s design and technology platform, said its N7+ process – which will use some EUV-imaged layers – should reduce area consumption by 10%. However, Northrop said while GF sees EUV as a potential vehicle for reducing manufacturing cost, it wants to minimise disruption to flows and is unlikely to alter the design rules.

One issue that foundries face is that EUV, although potentially a better lithographic technology, changes the process flows in those layers dramatically.

“From a lithography perspective, EUV is wonderful,” said David Fried, CTO of Coventor. “From a process-integration perspective, it has many implications.”