Imec enables 2D materials-based FETs for high performance logic

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The first material-device-circuit level co-optimisation of FETs based on 2D materials for high performance logic applications scaled beyond the 10nm technology node is said to have been demonstrated by researchers from imec, KU Leuven in Belgium and Pisa University in Italy.

Imec also presented novel designs that it claims could allow using mono-layer 2D materials to enable Moore’s law below 5nm gate length.

According to the company, 2D materials may be used to create the ultimate transistor with a channel thickness down to the level of single atoms and gate length of few nanometres.

“2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations. With advancing R&D, we see opportunities emerging in domains such as photonics, optoelectronics, (bio)sensing, energy storage, photovoltaics, and also transistor scaling,” said Iuliana Radu, member of technical staff at imec.

In their paper, the scientists presented guidelines on how to choose materials, design the devices and optimise performance to arrive at circuits that meet the requirements for sub-10nm high performance logic chips.

Their findings are said to demonstrate the need to use 2D materials with anisotropicity – having properties that differ based on the direction of measurement – and a smaller effective mass in the transport direction.

Using one such material, monolayer black-phosphorus, the researchers presented novel device designs that they claim could pave the way to extending Moore’s law into the sub-5nm gate length.

These designs reveal that for sub-5nm gate lengths, 2D electrostatics arising from gate stack design become more of a challenge than direct source-to-drain tunnelling