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ThreadX RTOS makes multicore development easier

Express Logic, a specialist in royalty-free rtos has announced the availability of its ThreadX rtos for the MIPS32 1004K coherent processing system (CPS).

Working with MIPS Technologies, Express Logic has developed ThreadX/SMP, an enhanced version of ThreadX designed to provide synchronous multicore support that preserves real-time responsiveness called 'Real Time SMP.'

According to Express Logic, ThreadX/SMP enables developers to take advantage of the significant performance boost of sharing the processing load over the multiple processor cores of the 1004K CPS while maintaining the real time responsiveness critical to embedded applications. Licensees of the 1004K CPS can now access the development and run-time solution for performance-intensive designs.

ThreadX/SMP is based on Express Logic's ThreadX RTOS, a small embedded OS designed to minimise system overhead and provide fast real time response. It is said to have a 10KB footprint and sub-microsecond interrupt response and context switch. Express Logic says ThreadX/SMP is suitable for demanding real-time applications where high efficiency and high performance are needed.

MIPS Technologies' 1004K CPS offers up to four processors, each with one or two virtual processor execution units (VPEs), and a unified shared memory accessible by all processors.

Express Logic uses this shared memory to design a symmetric multiprocessor version of the ThreadX RTOS that runs concurrently on all processors from a single copy in shared memory. Application processing is automatically distributed across the processors as processing demands dictate, so the developer does not need to be concerned with managing multiple processors.

Express Logic says that ThreadX/SMP achieves a high degree of ease-of-use by enabling multicore applications to be developed without needing to know the details of the 1004K architecture. ThreadX/SMP allocates and manages hardware resources to maximise application thread efficiency. It transparently maps application threads to individual cores within the 1004K CPS, providing automatic load balancing.

Author
Chris Shaw

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