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Simplified embedded system design with HyperRAM

A high-speed, self-refresh DRAM based on Cypress’ low pin count HyperBus interface is now sampling.

The 64Mbit HyperRAM serves as an expanded scratchpad memory for the rendering of high-resolution graphics or the calculations of data-intensive firmware algorithms in automotive, industrial and consumer applications. The device operates with a read/write bandwidth of up to 333Mbyte/s and is available in 3V and 1.8V supply voltage ranges.

When paired with a Cypress HyperFlash NOR flash memory, HyperRAM enables a simple and cost-effective solution for embedded systems where both the flash and RAM reside on the same 12 pin HyperBus. This reduces pin count by at least 28 pins compared to traditional systems with an SDRAM and Dual-Quad SPI solution, as well as decreasing design complexity and lowering PCB cost.

“With the rapidly growing usage of high-resolution graphics and data-intensive applications in a wide range of systems, we see a growing need in the market for a simple, high-performance DRAM that provides external scratchpad memory for controllers with limited onboard RAM,” said Rainer Hoehler, vice president of the flash business unit at Cypress.

Cypress offers a HyperBus Master Interface Controller IP Package to accelerate product design cycles. This controller IP helps designers add support for HyperBus to FPGA, ASIC or ASSP based platforms.

The devices will be available in a 24 ball, 6 x 8mm BGA.

Author
Peggy Lee

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