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First wireless clocks supporting 4G/LTE and ethernet

Silicon Labs has introduced a family of high-performance, multi-channel jitter attenuating clocks for 4.5G and Ethernet-based Common Public Radio Interface (eCPRI) wireless applications.

Using the company’s DSPLL technology the Si5381/82/86 clocks provide 4G/LTE and Ethernet clocking in a single IC. Highly integrated these clocks eliminate the need for multiple clock devices and voltage-controlled crystal oscillators (VCXOs) in demanding applications including small cells, distributed antenna systems (DAS) baseband units (BBU) and fronthaul/backhaul equipment.

As carriers transition to Ethernet-based eCPRI fronthaul networks to increase the capacity of fronthaul connections between base band units and remote radio heads, they are deploying heterogeneous network (HetNet) equipment at the edge of the network where cost, power and size constraints are proving challenging for hardware designers. By combining 4G/LTE and Ethernet clocking in a single IC, the Si538x family simplifies HetNet clock generation, providing what the company describes as a ‘breakthrough solution’ that is 55 percent lower power and 70 percent smaller than competing solutions.

The Si538x clocks are optimised to provide reference timing for HetNet equipment. Small cells and DAS equipment are “all-in-one” base stations that need reference timing for 4G/LTE transceivers, baseband processing and Ethernet/Wi-Fi connectivity.

The Si5386 clock’s low-phase-noise DSPLL replaces a discrete clock IC, VCXO and loop filter components in a compact, single-chip design. In addition, the Si5386 clock integrates five MultiSynth fractional clock synthesizers to provide simplified Ethernet and baseband reference timing.

Baseband units also have complex timing requirements requiring multiple independent clock domains for CPRI or links to remote radio heads, Ethernet-based eCPRI for fronthaul networks and general-purpose clocks for local baseband processing.

The Si5381/82 clocks combine a high-speed, low-phase-noise DSPLL supporting wireless frequencies up to 3 GHz with flexible any-rate DSPLLs optimized for Ethernet and general-purpose timing.

Like the Si5386 clock, the Si5381/82 devices require no external VCXOs or crystals. All PLL components are integrated on-chip in a space-saving 9 mm x 9 mm 64-LGA package. In addition, the Si538x clocks support a hitless switching capability that enables system designers to switch between different clock inputs and minimise phase transients, ensuring downstream PLLs remain in lock.

Author
Neil Tyler

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