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The right tools for the job

Designing a system on a programmable chip needs the right tools. By David Greenfield.

Advances in the size and speed of programmable logic devices (plds) and the accessibility of easy to use embedded processor cores and other IP are, by themselves, not sufficient to enable system on a programmable chip (SoPC) design. It takes a clearly architected system level methodology dealing with system level complexity to deliver the time to market benefits that pld technology enables.

In the past, pld customers benefited from the integrated aspects of tools such as MAX+PLUS II, an integrated design entity that included design entry, synthesis, simulation, place and route and timing analysis. Today, these same customers require use of best in class synthesis tools, best in class simulation tools and best in class timing analysis tools. Pld place and route tools must meet this changing requirement in a way that makes the entire design methodology look much more asic centric in orientation. If this new pld methodology is correctly architected, it will enable adoption of IP more quickly than asic technology could provide and support the flexibility and customisation that only programmable technology can deliver.

Download pdf version of the Altera Tutorial

Go to the Altera web site

Graham Pitcher

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