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The bigger picture

ESL approach improves asic and fpga based dsp design productivity. By Chris Eddington.

The use of digital signal processing in electronic products is increasing at a phenomenal rate. Field programmable gate arrays, with their multimillion equivalent gate counts and dsp centric features, can offer dramatic performance increases over standard dsp chips. They also offer an attractive alternative for small and medium volume production. Meanwhile, fpgas make very powerful prototyping and verification vehicles for real time emulation of dsp algorithms. However, there are areas of challenge and a requirement for creating portable algorithmic IP for both fpgas and asics.
Although rtl is portable at the logic level, it is not at the architectural level. If synthesised to a different target, the same rtl will yield less than ideal results; in a different target technology, the result may be functionally correct but not at all optimal.
Choosing algorithmic architectures involves the basic question of how much pipelining, parallelisation or serialisation is needed to meet the algorithm’s sample rate and throughput requirements. In addition, fundamental dsp functions – like FIR, FFT, sine, cosine and divide – may have different optimal implementations, depending on the target technologies. A good example is the direct form versus the transposed form of a FIR filter – one may be better for a particular fpga, whilst the other may be better for an asic.
Different architectures are usually required to get good results from an fpga versus an asic. FPGAs tend to be more register centric and many asic to fpga porting guidelines recommend lots of pipelining, registering of all ports and breaking combinatorial logic into smaller portions. This results in an area increase if done in the asic, but this might be required to meet timing in the fpga.

Chris Eddington

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