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Semiconductor industry pushes ahead to 7nm, even if EUV lithography isn’t ready

The semiconductor manufacturing sector's mission to conform to the demands of Moore's Law has begun to run into a number of significant barriers posed by physical properties.

One of these barriers has been the wavelength of light needed to enable the lithographic process. For some years now, the dimensions of the features on chips have been far smaller than the wavelength of light being used to create them. Some fancy footwork by production equipment developers has managed to overcome the apparent roadblock, but the day is coming when extreme ultraviolet (EUV) lithography needs to take over.

Burn Lin, vice president of Research and Development for TSMC, believes cost escalation at the leading edge is a serious issue. Explaining the dilemma facing chip makers, he said: "There comes a point when it costs too much to go to the next process node. To move forward, the value of the chip – for example, in terms of the better performance – has to outweigh the actual cost of making that chip."

Kurt Ronse, director of imec's advanced lithography programme, noted: "One of the big issues facing the industry when it comes to scaling beyond the 10nm node is lithography. It will become more and more complex and more and more expensive."

However, EUV continues to be delayed. Originally intended for use at the 45nm node in 2009, EUV is still very much in the R&D phase. Issues being addressed include the amount of power delivered by the tool; if the power figure is too low, not enough wafers can be handled per hour and the whole process becomes uneconomic.

This has meant the industry has had to resort to such 'tricks' as double patterning, where smaller features are created by 'stitching' together the exposures from masks with a larger feature size. As feature dimensions decrease, the number of patterns which need to be exposed increases. Already, there is talk of triple – and even quadruple – patterning. Again, cost becomes an issue – the more masks, the more expensive it is to make chips.

"The need for EUV has never been higher," Ronse observed. But it seems progress is being made. "At the recent EUV Symposium, encouraging results were being reported and the feeling is more positive."

One of the big issues with EUV is source power. "At SPIE in February, we were talking about a source power of 20W, but manufacturers are now saying that ASML's 3300 tool is generating between 50 and 70W," Ronse continued, "while TSMC says it has run a tool at 80W for 24hours." Yet even 80W is some way from being suitable for mass production. "The target has always been 250W," Ronse said.

While there is a major focus on EUV, another technology which has been in development for some years is multiple e-beam direct writing (MEB). With this approach, a large number of finely focused electron beams are used to alter the properties of a resist layer, allowing it to be removed selectively for further processing.

"MEB is quiet," Ronse said. "There was little discussion of the technology at SPIE and one presentation I saw didn't say anything new."

Lin said: "MEB needs to play catch up at the 7nm node due to its late start, insufficient funding and the industry's infatuation with EUV."

Ronse agreed: "There's little momentum. Investment is decided by manufacturers and if they don't see breakthroughs, they will forget about it."

While EUV and MEB appear to be the front runners, each has its own issues. Lin says the cost of EUV will be difficult to manage because the tool itself and the infrastructure are expensive, while productivity continues to be low. MEB cost is directly related to how many columns are used and how dense are the circuits being created.

Nevertheless, TSMC is pushing ahead with EUV and has ordered two NXE:3350B EUV systems from ASML for delivery in 2015. TSMC says it will use them in production and will also upgrade two existing EUV systems.

Meanwhile, imec is installing a 3300, replacing a 3100 running with a 4W power source. "Hopefully, this will be ready by February 2015," Ronse said. "It will have at least ten times the power of the 3100, which means we will be able to do a lot more work."

But despite all the work going into the development of lithographic technology, it could be that masks are the biggest issue on the road to smaller features, not the wavelength of radiation used.
For example, it is suggested that an EUV mask for a single layer could be more expensive than for a number of masks used to create the same features using multiple patterning immersion lithography.

More cost effective approaches are seen to be a mix of immersion lithography and either EUV or MEB. But the cost of immersion lithography is growing as the number of multiple patterning steps increases.

"There are points in the CMOS flow where EUV won't be applicable," Ronse accepted, "so there will continue to be a need for immersive lithography.

However, alignment accuracy becomes an issue with multiple patterning. The exposures need to be stitched back together so the original design is produced. "People are still pushing immersion lithography forward, but quadruple patterning will be too expensive, too complex. If you push it to 7nm, it will be even more of a problem."

And then there's the issue of resists. "They are a big part of the problem," Ronse conceded. "There hasn't been as much progress with EUV resists as had been expected, so the topic is now further up the list of critical issues. The source is still the most important, followed by reticules. But resist developments aren't keeping pace."

Pattern collapse is another challenge. While features are getting smaller, resist thickness isn't, which means the aspect ratio is increasing. "The accepted ratio is 3:1," said Lin. "If it's more than that, the resist may collapse or lean, affecting the image quality."

Ronse said Dry Development Rinse Material, or DDRM, is looking to be an effective solution to this problem. "There are groups working on other resist strategies, but it will take a couple of years for their work to mature. In the meantime, we have to find ways to work with current resists."

Will EUV make it? Ronse said: "The big question is whether EUV will be ready for 7nm or not. It will be extremely complicated without EUV because some stages might need five or six immersion exposures, compared to one or two with EUV.

"A call will be made at the end of 2015, so the industry has a year to solve the problems," he said. "But, at the recent EUV Symposium, Qualcomm said it will go ahead at the 7nm node, with or without EUV."

In Lin's opinion, while the lithography challenges for future process nodes are tough, they are worth addressing.

Author
Graham Pitcher

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