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NoC boost for SoCs

Packet processing concepts are beginning to find application in SoC interconnect. By John Walko.

Semiconductor suppliers may not agree on how to fix the problem, but all concur that on chip interconnects on increasingly complex SoCs are a bottleneck – and that devising cost effective solutions is a priority.
One approach is the Network on Chip (NoC) concept. Here, fixed buses are replaced with a packet based approach linked to a layered methodology – for instance, physical, transport and transaction layers. The concept thus brings such networking essentials as Quality of Service – which offers the possibility to predict latency and the arrival of packets – to the chip level.
There are, however, several NoC approaches. All provide the necessary point to point connections between any two hosts attached to the network, either by deploying true crossbar switches or through virtual point to point connections; they provide high aggregate bandwidth through parallelism; and they have implicit pipelining and thus provide intermediate storage for the data as it moves from sender to receiver.
But there are also differences. NoCs can be circuit or packet switched and there are numerous topology options, ranging from mesh networks to uni- or bidirectional rings.
On another level, companies are beginning to differentiate themselves by offering either an IP approach or one based on eda methodologies. And there is healthy debate whether to opt for synchronous or asynchronous synthesis.

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Author
Vanessa Knivett

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