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It's all in the timing

why have asic engineers embraced timing analysis whilst their board level counterparts have not? Rick Pier of Mentor Graphics explains why board level timing analysis has come of age.

In the past, few board design groups performed timing analysis. The consensus was that timing analysis at the board level offered little value and involved too much pain. Yet the technology is integral to the asic design flow. It is widely used as part of the asic sign off process and has, to a large extent, replaced gate level timing simulation.

Download pdf version of the Mentor Graphics Tutorial
Go to Mentor Graphics' site
Go to the Electronics Design site

Graham Pitcher

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