comment on this article

It's all in the timing

why have asic engineers embraced timing analysis whilst their board level counterparts have not? Rick Pier of Mentor Graphics explains why board level timing analysis has come of age.

In the past, few board design groups performed timing analysis. The consensus was that timing analysis at the board level offered little value and involved too much pain. Yet the technology is integral to the asic design flow. It is widely used as part of the asic sign off process and has, to a large extent, replaced gate level timing simulation.

Download pdf version of the Mentor Graphics Tutorial
Go to Mentor Graphics' site
Go to the Electronics Design site

Author
Graham Pitcher

Related Downloads
5085\mentor-9-jan-2001.pdf

Comment on this article


This material is protected by MA Business copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team.

What you think about this article:


Add your comments

Name
 
Email
 
Comments
 

Your comments/feedback may be edited prior to publishing. Not all entries will be published.
Please view our Terms and Conditions before leaving a comment.

Related Articles

Trust no-one

Over the past decade, concern has grown over hardware Trojans: malicious ...

Thermal evolution

Two years ago, a team of HP was faced with the challenge of getting more ...

Custom MMIC design

Plextek RFI CEO Liam Devlin discusses the technical and commercial ...

Between the layers

ZofzPCB is a free 3D Gerber viewer that allows designers to see inside the ...

Cloud Solver

Today, new technologies enter the market very, very quickly. For some of the ...

A digital revolution

The micro:bit Educational Foundation has been launched as a not-for-profit ...