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High Speed Digital Seminar 18th Sep, Cambridge and 20th Sep, Winnersh.

Learn how to successfully navigate through today's high speed technology challenges from early design to prototype validation whilst ensuring compliant designs.

When digital signals reach Gigabit speeds, "unpredictable" becomes the normal state of things. Getting your project back on track starts with the best tools and methodology for the job.

High Speed Digital Tour

Seminar | Where & When

When digital signals reach Gigabit speeds, "unpredictable" becomes the normal state of things. The process of getting your project back on track starts with the best tools and methodology for the job.

This seminar will guide you on how to successfully navigate through today's high speed technology challenges from early design to prototype validation whilst ensuring compliant designs.

Learn all about Signal Integrity challenges in High Speed Digital links and how you can anticipate and reduce these effects on your design.

Who should attend:

Engineers and Managers who are responsible for the design or test validation of complex PCBs and systems.

9:30 Welcome - A methodology for predictable design closure in the high speed digital era
9:45 Key Challenges in the analysis and design of high speed digital links
10:15 Closing the loop 1: Why use simulation tools for high speed signal channel design?

11:15 Break
11:30 Measurement fundamentals - High speed serial links, eye diagrams & jitter breakdown
12:00 Closing the loop 2: Measurement compensation & characterization: Virtual probing, model refinement

13:00 Lunch & Networking
14:00 A Day in the life of a memory system architect
15:30 Break
15:45 Xilinx (Maximising Serial Bandwidth And Signal Integrity In FPGAs)
16:45 From predictable design closure to protocol & compliance test automation

17:15 Summary and Close

Abstracts:
Key Challenges in the analysis and design of high speed digital links


This presentation will remind the key challenges occurring in High Speed Digital designs, such as Reflection, Crosstalk, Jitter, Power/Ground Noise and all types of signal degradation in the channel.

Agilent's high speed digital solution set is a range of both measurement and simulation tools that help you cut through the challenges of gigabit digital designs.

Closing the loop part 1: Why use simulation tools for high speed signal channel design?

Recent advancements in simulation technologies, design flow integration and modeling methodologies are enabling designers to develop new designs quickly and with confidence. This presentation will outline some of the key modeling, simulation and analysis technologies available within Agilent's ADS design environment as part of a typical enterprise PCB design flow solution, including the 'Fast Channel Simulator' which enables quick verification of a complete high speed channel.

The paper concludes with a demonstration of accurate SI effect prediction versus measurement of a simple but representative test PCB.

Why use Simulation Tools for High Speed Signal Channel Design?

The design of high speed signal channels is a complex activity. Recent advancements in simulation technologies, design flow integration and modeling methodologies are enabling designers to develop new designs quickly and with confidence.
This presentation will outline some of the key simulation and analysis technologies available to high speed channel designers within Agilent's ADS design environment, including the 'Fast Channel Simulator' which enables quick verification of a complete high speed channel. An important pre-requisite for any such channel simulation is the availability of accurate models to represent components within the channel, a review of the range of typical models required to construct the channel will also be presented and includes IBIS-AMI models for Tx/Rx, Pre-layout EM-based PCB interconnect models, Post-Layout EM-based PCB interconnect models and Measurement based models.

Measurement techniques of serial signals and fast rise time signals

When measuring fast rising signals or high speed data signals with an oscilloscope it is essential to use high-performance active probes, (otherwise known as low loading probes), which are electrically non-intrusive to your application. When selecting the probe and the best way to use it, engineers must consider all the attributes of a sensor - input impedance, bandwidth, linearity, connection accessories, ergonomics, etc.

This presentation discusses the measurement issues regularly encountered, and presents new techniques for solving them. We will also cover a wide range of related challenges such as jitter analysis and understanding the importance of noise.

Closing the loop part 2: Measurement compensation & characterization: Virtual probing, model refinement

Complex multilayer PCBs populated with densely packed BGA devices provide few opportunities to probe all of the signals that we might want to see and at the specific point on the high frequency transmission line that we want to see them. Simulation models of our system from the design phase can be reused to augment the reach of measurement instrumentation. In the reverse, Agilent's scope analysis interface can be taken off-line and out of the lab to provide designers with a window into the test engineer's world.

The topic concludes with a demonstration of how the measurement of various component and prototype parameters are used to refine the original simulation models for tighter accuracy.

With the "loop closed" between design and measurement the project is back under control and we now have the ability to quickly and predictably close the design.

A Day in the life of a Memory System Architect

The memory channel is found in a wide range of applications: PCs, notebooks and servers variously use DDR1/2/3 and RDRAM.

Some examples:
1) DDR3 can reach 17GB/s.
2) GDDR3/5 technology is widely used on graphic cards which add 3D rendering performance to PCs and game consoles. These can reach 20GB/s per GDDR5 component.
3) LPDDR2/3 are used for smartphones and tablets reaching 6.4GB/s with low power consumption down to 1.35V for maximum battery life.
Memory architects face a tremendous challenge in the design of a memory channel for each of these applications. They have found the optimum compromise between peak-bandwidth, power consumption and cost. To do this, successful designers use an advanced workflow and methodology supported by accurate modeling of each component of the memory channel. Unfortunately, one method can't do it all, so an integrated toolset is required: trace and via interconnects on PCBs and packages can be modeled quickly and accurately by applying a 3D multilayer full-wave EM solver that uses the method of moments, whereas connectors are best handled using 3D arbitrary geometry full wave methods such as finite element method (FEM). Cables are best modeled by measurement-based modeling using TDR or VNA measurements. I/O buffers can be modeled either using IBIS, IBIS-AMI or netlist-based models in the time domain. SSO noise generated from the memory devices is a wide-band phenomena that best handled using time-domain 3DEM tools such as FDTD. The goal is to eliminate the noise on power/ground planes that has deleterious effects such as synchronous switching noise and EMI violations. To comply with such EMI standards as FCC or CISPR it is better to fix the emission by designing the PDN correctly, rather than being force to use spread-spectrum clocking, because the latter impairs the memory channel performance.
Agilent Advanced Design System (ADS) offers a unique, integrated workflow consisting of circuit and channel schematics and simulation as well as 3D multilayer layout and MoM EM solver. In addition, ADS includes a patented convolution engine that lets you add frequency-domain models into a time-domain simulation for eye diagram and BER contour analysis. EMPro extends ADS with 3D arbitrary geometry drawing environment and FEM and FDTD EM solver.

From predictable design closure to protocol & compliance test automation

Once correlation is reached, it becomes possible to perform what-if analysis to explore design robustness by stressing the design to see how it handles different types of jitter. Automation of the compliance test process delivers significant TTM savings when exploring how close to margin and how ready for manufacture the design really is.

Beyond the electrical level, data signals are encoded with an embedded clock, so a signal needs post-processing to really understand how the design works at the software bring up phase. The seminar concludes with a quick look at complete solutions available for common protocol analysis providing visibility and triggering of payload data.

Register Now for the High Speed Digital Seminar

Author
Agilent Technologies

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