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Grasping the problem

Unified design flow is the answer to high speed serial interconnect design. By Larry Williams.

Engineers designing servers, storage devices, multimedia pcs, entertainment systems and telecom systems have driven an industry trend to replace legacy shared parallel buses with high speed, point to point serial buses.
Standard interfaces like XAUI, XFI, Serial ATA, PCI Express, HDMI and FB-DIMM have emerged to provide greater throughput using serial signalling rates of up to 10Gbit/s. Whilst this trend has reduced the number of traces and connections within the system, it has created new challenges for board designers when considering implementation using multiple connectors, transmission lines, vias, ic packaging and transceiver circuits. Reliable signal transmission across a host board or between daughter cards on a backplane at gigahertz rates compel the adoption of new strategies and tools.
Although traditional electronic design automation (eda) tools can be used for some channel analyses, traditional design solutions with disparate solvers – disconnected from one another – create challenges for design management and are highly error prone.
Hence, recognising that a unified design flow would be needed to model modern multi gigabit transmission – one that included physics based models for interconnects combined with advanced circuit simulation technology – Intel teamed with Ansoft to define just such a reference flow. The joint effort leveraged Intel’s expertise in designing and developing high speed serial interconnect and standards and Ansoft’s expertise with advanced circuit simulation and electromagnetic extraction tools.

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Vanessa Knivett

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