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Good things in small packages

How a new approach to packaging is meeting a wide range of needs.

Packaging semiconductor devices is becoming a challenge for the industry. As process technologies become smaller, so too do the devices which are being made on those processes. And interfacing the chip to the outside world becomes equally problematic.

Pressure is also being applied from end users. Mobile phone developers, for one, are looking for devices that not only have the minimum footprint possible, but which also are as thin as possible.

Andreas Bahr is director of cooperations and licensing for Infineon Technologies' packaging developments. He said: "We had the intention five years ago of advancing packaging technology to the point where we could reuse most of the equipment. The driver – especially for mobile phone customers – was to reduce cost. One way in which we thought we could do this was by getting rid of the lead frame, leaving the basic carrier and connecting via flip chip or wire bonding."

The idea that was developed took a silicon wafer and diced it. But instead of then encapsulating the resulting dice individually, the process rearranged the chips into a matrix similar in format to a 200mm wafer. "The aim of this was to reuse all of our existing front end equipment," Bahr continued.
The approach has since been named embedded wafer level ball grid array technology – or eWLB.

Infineon has since joined forces with STMicroelectronics and back end processing company STATS ChipPAC to develop the approach.
eWLB technology uses a combination of traditional front end and back end semiconductor manufacturing techniques with parallel processing of all the chips on the wafer, leading to reduced manufacturing costs. This, says Infineon, together with the increased level of integration of the package and a greater number of external contacts, means the technology can provide cost and size benefits.

The eWLB project is addressing a wide range of factors. At one end of the spectrum is the packaging cost to which Bahr alluded, along with testing costs. Alongside these are physical constraints such as its footprint and height. Other parameters which were considered during the development phase included: I/O density, a particular challenge for small chips with a high pin count; the need to accommodate systems in package approaches; thermal issues related to power consumption; and the device's electrical performance, including parasitics and operating frequency.

The obvious solution to the challenges was some form of wafer level packaging (WLP). But two choices presented themselves: fan in or fan out.
Fan in WLP is an interconnection system processed directly on the wafer and compatible with motherboard technology pitch requirements. It combines conventional front and back end manufacturing techniques, with parallel processing of all chips.

There are three stages in the process. Additional fab steps create an interconnection system on each die, with a footprint smaller than the die.
Solder balls are then applied and parallel testing is performed on wafer. Finally, wafers are sawn into individual units, which are used directly on the motherboard without the need for interposers or underfill.
According to Infineon, this approach should not be confused with bumped flip chip devices, which have a finer pitch, smaller bumps and which need underfill.

eWLB, meanwhile, is a fan out process. The die is surrounded by a suitable material, which spreads the package footprint outside the die. Tested good dice are embedded in an 8in diameter plastic wafer using a proprietary technique.

Front end isolation and metallisation processes are then used to fan out
the interconnections to surrounding area. Again, solder balls are applied and parallel testing is performed on wafer. The reconstituted wafer is then sawn into individual units, which are packed and shipped.
With the fan in approach, the number of interconnects and their pitch must be adapted to the chip's size. eWLB, by contrast, supports a fan out area which is adaptable and which has no restriction on ball pitch.

Bahr explained the eWLB process. "We apply a dielectric copper layer for routing, then attach solder balls. The reconstituted wafer is then diced. The final product looks like an existing bga and the customer will see no difference. But from the production perspective, we are getting rid of the laminate layer; the most expensive part of the package."
He says package cost is one part of the approach. "Silicon is getting smaller and smaller, which means you are getting a lot more chips from a 300mm wafer. Because of this, package cost is becoming more significant."

Carlo Cognetti is ST's package development director. He said ST had approached the packaging problem from a slightly different direction. "We saw the current technology platform – the bga – getting closer to its limitations, especially with regard to the substrate. Moving to eWLB overcomes those limitations. It's a next generation platform that will support future integration, particularly for wireless devices."
BJ Han, chief technology officer for STATS chipPAC, said the packaging technology had a number of important features. But one of the most important is eWLB's potential ability to 'future proof' packaging technology.

"The problem with technology nodes beyond 65nm," he noted, "is the dielectric material in chips is getting weaker. As a result, a lot of technology is switching. There is the need to go beyond wire bonding to some kind of flip chip. But the fine pitch in flip chip is becoming narrower in terms of process margin, making the situation worse. Added to that is the green movement, with the move away from the use of lead.
"With ultra low K pitch becoming smaller and smaller and with lead free not going away, the technical limitations we face are becoming more challenging. eWLB gives us a 'window' for packaging next generation devices in a generic, lead free scheme."

But eWLB, as it stands, has its limitations: it's a one side, one layer technology at the moment. That apparent limitation is set to be addressed in an extension to the collaboration between the three companies. This r&d effort will focus on using both sides of the reconstituted wafer to provide a higher level of integration, as well as more contacts.
Cognetti observed: "We are pleased with the technology, but it's still first generation. We want to exploit the approach by, for example, handling multichip packages and we see good synergy with 3d ic technology."
eWLB has, so far, been qualified as an 8 x 8mm package with a 0.5mm solder ball and a 5 x 5mm die size. Typical thickness is 0.8mm.

In the next generation of eWLB, both sides of the reconstituted wafer will have isolation and metal layers, connected using conductive vias. More than one metal layer can be included and package size will be increased to 12 x 12mm, with thickness reduced to 0.5mm. And it may be possible to embed more than one chip.

Han was keen to point out that eWLB was not 'reinventing the wheel'. "It is important because we need some way of making finer pitch, lead free devices. Nothing today gives us this path and we're really optimistic," he concluded.

Graham Pitcher

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