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Getting on the right track

Some tips on how to design high quality load boards matched to fine pitch devices. By Nigel Rowe.

Ever increasing ic complexity, shrinking geometries and high pin count packaging forms are fast eroding positional and performance safety margins during semiconductor test. This reduced room for manoeuvre will force ic designers to invest more effort into design for test (DFT).
Fortunately, DFT using leading edge silicon is not as difficult as it may first appear. By taking into consideration just a handful of ‘rules’, 90% of the problems can be avoided.
As a firm that specialises in providing load boards for semiconductor testers, Shane is fortunate in that it gains early visibility of next generation packages and devices and the test challenges they create. For example, we are already being asked to develop test boards for 0.3mm pitch ball grid arrays (bgas). Such packages must be designed from the outset to support high speed silicon fabrication and verification testing, otherwise it becomes increasingly difficult to resolve test problems without major redesigns.

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Nigel Rowe

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