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ESL packs power

The standards and tools are emerging to enable true electronic system level design. By Louise Joselyn.

Electronic system level (ESL) design was initially hailed as the replacement for hardware design languages (hdls) in complex asic, SoC and fpga design. That was a mistake. Designers working at the rtl level – comfortable using Verilog and Vhdl – took fright, though they knew something had to be done to tackle increasing complexity and decreasing productivity.
Today, ESL design is increasingly regarded as an essential part of the chip design flow. Industry standards are slotting into place, methodologies have been tried and tested and more practical tools are emerging.
IP reuse is considered by most designers of asics, SoCs and large fpgas as vital to achieve productivity gains. The impact, however, is an increasing emphasis on architectural level design and, with it, the need to work at a higher level of abstraction. It has also resulted in a huge escalation in the amount of verification required – particularly at the functional level – and this requires new models.
Meanwhile, ensuring software development schedules dovetail with hardware design has become a major challenge, especially with ever more system functionality on chip and longer design times. Yet time to market targets are relentless.
SoC and fpga designers are finding a solution to these challenges in the adoption of an ESL design methodology. The earlier barriers are falling as standards coalesce and new tools appear from comparatively new companies. The array of standards and tools may bewilder the newcomer, but there is evidence the approach is working.
So what is ESL design? The essential premise is the use of SystemC – particularly for transaction level modelling (TLM) – enables very fast simulation, which serves to speed functional verification and architectural exploration and modelling. Importantly, this higher level simulation is fast enough to be useful to software developers.

Louise Joselyn

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