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Countering complexity

How are eda companies responding to the need to design high pin count packages onto pcbs? By Louise Joselyn.

High pin count packages are becoming increasingly popular. No longer reserved exclusively for specialist parts, commodity devices – including multichip memories and fpgas – are available in 1500pin bgas and 3000pin bgas are not uncommon.
Technologies such as system in package (SiP) are also gaining ground. Philips, for example, offers highly complex devices containing multiple die. SiPs have also found favour for devices requiring sensors combined with digital cmos circuitry and are finding application in the automotive and security markets.
From one perspective, these highly integrated devices can reduce board level design complexity, as interconnection between the rf and digital sections, for example, is achieved inside the chip. But there are still problems to solve when placing high density devices on boards. As a result, new board fabrication techniques, such as fine line HDI and multilayers with micro vias, are emerging.
Whether or not such techniques are adopted, signal integrity remains a primary concern at board level. The potential for interference between devices on a chip requires careful consideration and analysis. Poorly designed or attributed pin outs can cause major headaches, incurring unnecessary delays and costs. A detailed understanding is required of pin assignment at the chip level and its effect on board level design, especially for routing related timing performance. Poor interaction can result either in errors in the fpga or a board respin.

Louise Joselyn

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