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Complex devices require complex packaging

Packaging a semiconductor component is becoming an increasingly complex business. It's never been an easy task, even for simple devices, but when it comes to leading edge products, there is more than a degree of boundary pushing involved.

Dr Babak Sabi is director of assembly and test technology development for Intel. A 30 year Intel veteran, Dr Sabi assumed responsibility for packaging and packaging materials, as well as assembly and test, in 2009. During the past five years, he's overseen the packaging of a range of leading edge devices, such as Intel's Xeon and CoreM processors.

"We design the majority of packages for our products in house," he noted. "However, there are some products for certain market segments where we use outside assembly and test services, or OSAT. In some cases, we use industry standard packages, but we will design our own packages where necessary. If we do use a commodity package, we have a strong benchmarking process in house that allows us to make sure it meets our needs."

The benefit, according to Dr Sabi, is that Intel retains the ability to optimise the silicon package and the board onto which the chip goes. "We take a holistic view at the system level," he continued, "to optimise a wide range of parameters to find the most economic way to deliver the performance, quality and reliability which we desire. But our emphasis is on the economics because high performance at high cost is not the desired outcome; we have to optimise all vectors to achieve the solution."

With every process shrink, the cost of the package increases as a proportion of overall cost. "It does depend on the market being targeted," Dr Sabi said. "If you a planning a big package, it can be up to 20% of the overall cost. For a complex product aimed at servers, for example, the package will represent 20% of device cost."

One of the most recent packaging projects which Dr Sabi has overseen is the move to the next generation of the Core processor range (see fig 1). The 22nm variants are based on the Haswell microarchitecture, while Broadwell represents a process shrink to the 14nm node. "In moving from one generation to the next," he said, "the package area has been reduced by 50% and the device thickness by 30%. The packages are sometimes more than what you would call transformative."

The process shrink brings a smaller die size – not only in area, but also in thickness – which means the challenges involved in bringing power to the die and routing data to and from it increase. "As we get into advanced silicon," Dr Babi continued, "we need to make sure the packaging material and processes are optimised."

One of the packaging developments which have been applied to so called Broadwell devices is the use of a 3D approach (see fig 2). Here, inductors have been removed from the package substrate and placed on what Intel calls 3DL modules and mounted in a special recess underneath the die. "We have created a hole in the processor's motherboard to ensure the Z height is not impacted by the required capacitors and so on. The 3DL module is placed right behind the die, which provides the most direct path to deliver power efficiently."

Z height, over the years, hasn't been a great concern for chip developers, the advent of ultra thin consumer devices has begun to make this an important parameter.

"There are limits to how thin the package can be. If you look at devices for use in mobiles phones, for example, Z height is really important," Dr Sabi observed. "It's about 1mm at the moment, but we know we can make devices thinner if that is required. However, the thinner the device becomes, the more likely you are to run into problems such as warpage, so you get to the point where the package doesn't need to be any thinner."

He said it is also possible to start from the requirements of an end product – a tablet, for example – and understand the Z height target. "We can work our way backwards, but we have to consider that some products may need a thermal solution attached to the silicon."

Both the Haswell and Broadwell motherboards house two chips (see fig 1). "We have to make sure the connections between the two dice are good so they can link together. We have to put the memory channels at a place where it's easy to connect."

So what comes first: the die or the package? "Where a device has simple functionality, package design follows die design," he observed. "However, at the other end of the spectrum, where there is a very high level of integration, with multiple dice and multiple functionality, then the package and the silicon it encloses have to be optimised from day one: the whole floorplanning process happens at the same time. We have to put the I/O in the best place for routing and define the location of signals early in the design."

In Dr Sabi's opinion, Intel is one of largest developers of multidie chips. "This approach brings definite advantages," he noted, "but it does depend on what you're trying to accomplish."

Is the packaging material 'any old plastic'? "It depends on the application," he responded. "In some cases, where there's a lot of high speed signals and high frequencies, we have to use special materials which we have developed in association with our suppliers. When there's a need for low attenuation, we have to get involved in materials development with substrate suppliers."

But Intel has no interest in ceramic packages. "We stopped using ceramic in 1995," Dr Sabi asserted, "and we have no intention of going back. Ceramic packages have their own design rules and cannot support modern chips. We can meet all our application requirements with plastic." One of the issues with ceramic packaging is the use of tungsten. "That's very difficult to dimension," Dr Sabi explained. "Copper is much better."

Another aspect of packaging design that is not always obvious is heat removal. "It's extremely important," Dr Sabi noted. "When the processor goes into service, users want an efficient way of extracting heat from the silicon. A typical server package will have a huge number of high speed signals and extreme power delivery requirements. The more efficient the heat removal, the better the chip will perform."

These devices integrate the largest pieces of silicon which Intel designs. According to Dr Sabi, processors such as the Xeon E7v2 have a die measuring 45 x 45mm. "In some instances, it's 55mm square.

Good thermal performance for the Core M processor means the devices can enable the development of fanless 'two in one' devices with a thickness of less than 9mm.

While Intel is currently exploiting 2.5D packaging techniques, it won't be long before this moves to 3D. "The whole industry is working on 3D packaging," Dr Sabi concluded, "and it's in development right now."

Graham Pitcher

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