Technology Filtered by - Interface/Interconnect

New Electronics strives to bring you all the latest technology news from the Interface/Interconnect sector. Advances in electronics are often fast-paced and innovative, so we know that as a design engineer you want to be kept up-to-date with current developments.

Below is a comprehensive list of all the latest electronics technology news from New Electronics.

A matter of protocol

Serial communications: system requirements and design challenges. By Nilam Ruparelia. By the late 1990s, as Moore’s Law continued to deliver semiconductor integration and processing power, high bandwidth chip connectivity had become a significant bottleneck. It quickly became clear that, if the industry did not figure out ways to increase data transfer rates among high performance logic chips (like cpus, wan framers, dsps and network processors), it would end up with many thousands of pins on each multimillion gate device. High speed serial communication surfaced as the obvious solution and cmos technology, at geometries of 0.18um and smaller, enabled integration of high speed plls and I/Os in standard logic chips. Unfortunately, the enthusiasm for high speed serial communication resulted in a plethora of confusing serial protocols. A large number of protocols addressed the ‘sweet spot of 1 to 3.2Gbit/s. To make matters worse, some six other protocols surfaced in the 2.5 to 3.2Gbit/s serial rate range. At first glance, it may seem an abundance of standards would mean a fragmented market, or that a lot of energy was being spent primarily on I/O, but most protocols cater to specific applications. It is useful to understand how system level requirements make one protocol more applicable than another for a particular application. Similarly, we can glean useful information from board design challenges related to signal integrity issues, helping to prepare us for next generation protocols and system designs at 5 to 10Gbit/s.

The eyes have it

High speed serial communications links need to be designed and tested carefully. By Graham Pitcher. It wasn’t long ago that data communications was a relatively simple design task. Today, all that has changed. To meet the demand for higher and higher data rates, designers are moving to serial data links. Along the way, they are having to deal with some fundamental physical issues. Yves Braem is a signal integrity engineer with Tyco Electronics’ circuit and design department (www.tyco.com). He said: “With higher data rates, the problems you encounter become more and more significant. As frequency increases, transition times get smaller and the electrical waveform ‘sees’ the transmission path in ever more detail. This means you have to design carefully.” In Braem’s opinion, high speed data links bring an increasing number of signal integrity problems as data rates move beyond 2.5Gbit/s. “Designers not only have to select reliable and first class components and interconnections, they also have to consider the interfaces between the different ‘building blocks’ in the system.” In his view, these interfaces used to be electrically short because the signal wavelength was much bigger than the component itself. “Now,” he continued, “the interface itself can jeopardise the whole interconnection quality.” He believes three aspects need to be considered when designing high speed backplanes: pcb traces; connector/board interfaces; and board to board connectors. “The throughput of signal traces in pcbs is limited by trace losses, consisting of skin effect and dielectric losses,” he noted. These losses combine to limit the total trace length in the system and, therefore, system size. Dielectric loss can be reduced by specifying low loss pcb materials, whilst skin effect losses are reduced through the use of wider traces. But designers may not be able to specify wider because of space constraints and other factors.

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