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Architecting the future

Test chips: a critical success factor for nanometer design and manufacturing. By Narain Arora.

Semiconductor device shrinks have pushed interconnect delay to the forefront of the timing calculation issue, where transistor switching delay once dominated. Because resistance and capacitance drive interconnect delay, they must be measured and characterised accurately. Moreover, copper and low k dielectrics have introduced new 3d structures that must also be measured, analysed and modelled carefully.

The only way to achieve accurate modelling and characterisation of interconnect wires and to ensure data accuracy for the expensive mask sets required for new generation devices is through the test chip. These chips are, therefore, crucial to design for manufacturability (DFM), as they enable chipmakers to verify the quality and reliability of design rules prior to mass production.

This is particularly important when implementing new interconnect architectures. One such example – the X Architecture – targets ics with five or more metal layers, rotating the primary direction of the interconnect in the fourth and fifth metal layers by 45° in relation to conventional orthogonal, or 'Manhattan', architecture (see Figure 1). This diagonal routing reduces wire length by an average of 20% and via count by an average of 30% – while improving chip speed, area, power and cost. Additionally, maintaining orthogonal interconnection on the first three layers preserves designers' investment in cell libraries, memory cells and compilers, datapath compilers and IP cores.

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Graham Pitcher

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