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A matter of protocol

Serial communications: system requirements and design challenges. By Nilam Ruparelia.

By the late 1990s, as Moore’s Law continued to deliver semiconductor integration and processing power, high bandwidth chip connectivity had become a significant bottleneck. It quickly became clear that, if the industry did not figure out ways to increase data transfer rates among high performance logic chips (like cpus, wan framers, dsps and network processors), it would end up with many thousands of pins on each multimillion gate device. High speed serial communication surfaced as the obvious solution and cmos technology, at geometries of 0.18um and smaller, enabled integration of high speed plls and I/Os in standard logic chips.
Unfortunately, the enthusiasm for high speed serial communication resulted in a plethora of confusing serial protocols. A large number of protocols addressed the ‘sweet spot of 1 to 3.2Gbit/s. To make matters worse, some six other protocols surfaced in the 2.5 to 3.2Gbit/s serial rate range.
At first glance, it may seem an abundance of standards would mean a fragmented market, or that a lot of energy was being spent primarily on I/O, but most protocols cater to specific applications.
It is useful to understand how system level requirements make one protocol more applicable than another for a particular application. Similarly, we can glean useful information from board design challenges related to signal integrity issues, helping to prepare us for next generation protocols and system designs at 5 to 10Gbit/s.

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Vanessa Knivett

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