Wafer pruning set to improve chip manufacturing yields

Puneet Gupta, professor of electrical engineering, UCLA

Looking to improve semiconductor manufacturing yields, Semiconductor Research Corporation and researchers from University of California, Los Angeles have developed a method of monitoring semiconductor wafers that may lead to less expensive chips with higher performance.

The method – called wafer pruning – performs wafer tests earlier in the manufacturing process, rather than after chip packaging. By using process monitors on wafer lines tested after the initial manufacturing steps, manufacturers can evaluate die performance earlier and estimate wafer yield.

"The notion of design assisted manufacturing is a big change from the way things are done currently," said Puneet Gupta, pictured, professor of electrical engineering at UCLA. "Our research provides a way to not waste resources in producing silicon wafers that will eventually lose money because chips on them are not good enough for production. We believe that the cost reductions from this and other design-assisted manufacturing methods that we are investigating could easily be as much as one full technology node."

The researchers are currently fine tuning the approach, which includes a 45nm silicon prototype.
For more on fault tolerant design and the drive to improve yields, click here.

Author
Graham Pitcher

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