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Siemens extends EDA support for Samsung process technologies

Siemens Digital Industries Software has enabled several of its electronic design automation (EDA) product families for the latest versions of Samsung Foundry’s advanced processes.

These include Siemens’ solutions targeting advanced packaging, electrostatic discharge (ESD) rules and integrated circuit (IC) design in the cloud.

“Samsung Foundry is pleased to work closely with Siemens, which continues to increase its value to the Samsung Foundry ecosystem by offering more features in support of our latest processes,” said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics.

Samsung has successfully evaluated Siemens’ digitally integrated High Density Advanced Packaging (HDAP) flow for the foundry’s MDI (multi-die-integration) packaging process. For customers, this optimisation helps enable seamless integration across multiple dies through construction of the complete MDI package assembly, allowing customers more choices on how to deliver new products to market on time and with greater performance and quality.

The Siemens tools successfully evaluated include:

  • The Xpedition Substrate Integrator software, which Samsung used to generate a top-level “golden” system netlist for 3D LVS verification with
  • Calibre 3DSTACK software. This netlist delivers foundry qualified sign-off MDI heterogeneous 3.5D structures.
  • Xpedition Package Designer, which Samsung evaluated for physical implementations of its 3.5D Silicon Interposer. This is a first for a package design tool targeting Samsung’s MDI technology, and it enables early-stage PSI (power and signal integrity) analysis in connection with Siemens’ HYPERLYNX suite of tools.
  • HYPERLYNX, which supports PSI analysis of SerDes and HBM (high bandwidth memory) channels implemented on Samsung’s 3.5D Silicon Interposer.
  • The Calibre xACT 3D software and Calibre xL parasitic extraction tools, which quickly and accurately extract RCLK parasitics in highly complex 2.5D and 3D packaging configurations. The Calibre parasitic extraction tools help enable signal integrity-aware analysis of the entire HBM channel implemented on the 3.5D Silicon Interposers.

Verification for design compliance with foundry electrostatic discharge (ESD) rules is a critical step in the design tape out process and demands an extremely robust physical reliability platform.

Siemens’ Calibre PERC software’s advanced algorithm development functionality, parallel compute capabilities, and automated context-aware architecture have slashed the runtime of full chip ESD verification by half while maintaining accuracy, improving verification quality, increasing checking coverage, and allowing for world-class speed in new kit development.

Working closely with Samsung, Siemens has developed a flow capable of being automated from a single configuration file. This flow can rapidly generate verification kits for different technologies and with minimal development effort.

Samsung Foundry is the first foundry globally to leverage the parallel compute capabilities of Calibre PERC in their ESD checking solution.

Siemens and Samsung have also developed best practices for design teams looking to leverage cloud scaling for even faster physical verification run times. These best practices include setting up batch Calibre nmDRC runtimes, in addition to other Calibre products that design teams might choose to run, such as Calibre SmartFill software, once they have placed their design on the cloud.

Author
Neil Tyler

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