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MIPS selects Imperas Reference Models for RISC-V processor verification

Imperas Software, a leader in RISC-V simulation solutions, has together with MIPS announced the continuation and extension of its long-standing relationship with simulation and verification support for RISC-V.

Since 2010 MIPs, the processor technology company which is focused on the commercialisation of RISC-based processor architectures and IP cores, has partnered with Imperas for proprietary simulation technology and reference models for both internal engineering and customer ISS solutions. As the design and verification team transitions to the RISC-V open ISA (Instruction Set Architecture), the Imperas reference models for RISC-V form the reference for the processor functional verification tasks.

The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model encapsulated within a SystemVerilog environment. This covers asynchronous events and offers a seamless, time-saving transition to debug analysis when an issue is found.

Since the main role of a central processor is to execute software, software plays a major role in the complete design cycle from the initial project concept to the detailed functional verification, and in the case of processor IP, beyond into the final SoC design and end application development.

SoC developers select processor IP based on many factors, however, one of the key deliverables that supports the ease of use is a high-quality ISS to support software development.

Since 2010, the MIPS core IP deliverables have included the Imperas based ISS, and as a consequence Imperas technology has helped to support many projects in applications such high-performance wireless communications, networking, automotive and AI applications, with major customers including MediaTek and Intel Mobileye.

“As the MIPS design and verification teams transition to RISC-V, we see a lot of benefits from adopting the open ISA specification,” said Don Smith, Director of Engineering at MIPS, Inc. “As an IP company, we have a significant focus on the quality and verification of our processor IP deliverables. Imperas are the leaders in RISC-V simulation and verification and, with more than a decade of collaboration, they are the obvious DV partner for MIPS and its new RISC-V offerings.”

“RISC-V is at the forefront of a hardware design renaissance in optimized processors,” said Itai Yarom, VP of Sales and Marketing at MIPS, Inc. “But, an ISA only provides the envelope of possibilities. The art and science of processor optimisation requires complete feature exploration and verification, which are supported by the reference model simulation and verification technology from Imperas.”

“The Imperas simulation technology has two unique attributes, it models processors with the accuracy, control, and visibility required for functional DV and secondly, it can be integrated into all the main EDA verification environments.” said Simon Davidmann, CEO at Imperas Software. “Integrating our RISC-V reference models into a SystemVerilog UVM testbench supports the latest techniques for asynchronous events with ‘step-and-compare’, and provides a single environment to efficiently resolve issues.”

Author
Neil Tyler

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