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Making RTL verification easier

Codasip, a supplier of customisable RISC-V embedded processor IP, and Metrics Design Automation, a provider of the True Cloud EDA solution, have announced the integration of Metrics’ SystemVerilog RTL Simulation Platform within Codasip’s Pro SweRV Core support package.

According to the announcement, the integration will provide an easy-to-use and inexpensive way for ASIC designers to verify modifications and enhancements they make to the SweRV embedded processor IP.

One of the major benefits of the open source RISC-V ISA is that it allows users to customise their processor IP for optimal implementation in domain-specific applications. However, this comes with the responsibility to verify any changes made to the processor IP for functional accuracy. Codasip and Metrics have teamed up to address this requirement by making RTL verification available in the Cloud directly from the Codasip SweRV Core support package. As a result, SweRV and the support package users do not have to install and license any EDA software, do not have to make any expensive purchases of RTL simulation software, and have all the SweRV and verification IP required preloaded in a Cloud cluster for immediate use.

“Codasip continues to expand its ecosystem for RISC-V embedded processor IP,” said Karel Masařík, CEO of Codasip. “This integration of the Metrics Cloud Simulator in our SweRV Core support package is an example of making RTL verification easier and more affordable for Codasip customers and SweRV users.”

The Metric Cloud Simulator is a fully compliant SystemVerilog simulator and is the only RTL simulator available with a SaaS business model - users simply pay for use as a service.

The implementation of Metrics simulator in the Cloud will help to provide massive scalability so regression tests can run in parallel and can be completed in a matter of hours, not days.

“The popularity of RISC-V and in particular the SweRV open source processor IP has been impressive,” noted Doug Letcher, CEO of Metrics. “We are excited to partner with a leading RISC-V embedded processor IP vendor such as Codasip to deliver better usability, accelerated verification, and much more affordability of RTL simulation tools to the ASIC and SoC design community.”

The SweRV Core support package with Metrics Cloud Simulation integration is now available.

Author
Neil Tyler

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