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FPGAs offer 'unprecedented mix'

Lattice pushes FPGAs into complex pld market

Lattice says the MachXO2 family of programmable logic devices (plds) will offer an 'unprecedented mix' of low cost, low power and high system integration.

Built on Fujitsu's low power 65nm embedded flash process, the family delivers a threefold increase in logic density, 10 times more embedded memory and more than 100 times reduction in static power compared to Lattice's MachXO plds. Functions such as user flash memory, i2c, spi and timer/counter have been hardened to save look up tables (LUTs).

"Through the use of 65nm embedded flash technology, we have reduced costs and increased functionality, while dramatically reducing power consumption," said Gordon Hands, director of marketing for low density and mixed signal solutions.
T
he MachXO2 family offers three options. The 1.2V ZE devices range from 256 to 7k (LUTs) and run at up to 60MHz. HC devices also feature from 256 to 7k LUTs, but operate from 2.5 or 3.3V supplies while running at up to 150MHz. Finally, 1.2V HE parts will be available with 2 to 7k LUTs and run at up to 150MHz.

The three variants can be produced using a single mask set designed to work with two doping schemes. "It's the first time it's been done by Lattice," said Hands, "and I suspect it's the first time it's been done in the industry."

Other innovations include triple staggered I/O pads and asymmetric I/O banking.

Author
Graham Pitcher

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