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First complete IP solution for PCI Express 6.0

In a world first, Synopsys has announced the first complete IP solution for the PCI Express (PCIe) 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs.

Built on Synopsys' widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state.

Synopsys' complete IP solution looks to address evolving latency, bandwidth and power-efficiency requirements of high-performance computing, AI and storage SoCs.

In order to achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design.

The Controller, with available 1024-bit architecture, allows designers to achieve 64 GT/s x16 bandwidth while closing timing at 1GHz. In addition, the controller provides optimal flow with multiple data sources and in multi-virtual channel implementations.

To facilitate accelerated testbench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customised with minimal effort.

Synopsys' DesignWare PHY IP for PCIe 6.0 provides unique adaptive DSP algorithms that optimise analogue and digital equalization to maximise power efficiency regardless of the channel. The PHY enables near zero link downtime using patent-pending diagnostic features. The placement-aware architecture of the DesignWare PHY IP for PCIe 6.0 reduces package crosstalk and allows dense SoC integration for x16 links. The optimised datapath with ADC-based architecture achieves ultra-low latency.

"Advanced cloud computing, storage and machine learning applications are transferring significant amounts of data, requiring designers to incorporate the latest high-speed interfaces with minimal latency to meet the bandwidth demands of these systems," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "With Synopsys' complete DesignWare IP solution for PCI Express 6.0, companies can get an early start on their PCIe 6.0-based designs and leverage Synopsys' expertise in PCI Express to accelerate their path to silicon success."


Author
Neil Tyler

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