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DDR5/LPDDR5 IP solution on TSMC N5 process technology

Cadence Design Systems, has announced the availability of a complete, silicon-proven IP supporting the DDR5 and LPDDR5 DRAM memory standards on TSMC N5 process technology.

The multi-standard IP includes Cadence PHY and controller Design IP and Verification IP (VIP) and supports a wide variety of applications including data centre, storage, artificial intelligence/machine learning (AI/ML) and hyperscale computing. Customers using Cadence and TSMC technologies can design advanced-process chips that connect to multiple memory types more quickly and with low risk.

The bringing together of DDR5 and LPDDR5 protocol solutions in the same memory interface IP offers a high-speed, scalable solution from large to small memory footprints. The goal of this Cadence IP is to make DDR5 and LPDDR5 implementation predictable and successful and to make it a flexible solution.

The multi-standard DDR5/LPDDR5 IP solution allows users to use a single chip to support multiple memory types in different environments, enabling their chips to be used in different markets and products with different DRAM requirements.

“We’re pleased to see the delivery of Cadence’s DDR5/LPDDR5 IP on the TSMC 5nm process technology, which is optimised for the latest emerging application areas,” said Suk Lee, Senior Director of the Design Infrastructure Management Division at TSMC. “Through our continued collaboration with Cadence, we’re enabling mutual customers to design with these solutions, benefiting from the remarkable performance and power boost of our most advanced process technology and quickly launching their new product innovations to market.”


Author
Neil Tyler

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