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Collaboration looks to accelerate hyperscale computing SoC design

Cadence Design Systems has revealed that it has optimised the Cadence digital 20.1 full flow for Samsung Foundry’s advanced-process technologies down to 4nm.

As a consequence of the company's collaboration designers can now use Cadence tools to achieve optimal power, performance, and area (PPA) and deliver accurate, first-pass silicon for hyperscale computing applications.

Cadence's digital 20.1 flow is able to provide capabilities that are well-suited for Samsung Foundry’s advanced-process technologies. For example, the iSpatial technology allows a seamless transition from the Genus Synthesis Solution to the Innovus Implementation System using a common user interface and database.

Machine learning (ML) capabilities enable users to also leverage their existing designs to train the GigaOpt optimisation technology to limit design margins versus traditional place-and-route flows.

Combined with a high-performance clock mesh architecture, the digital GigaPlace XL technology offers concurrent macro and standard cell placement that enables automated floorplanning, delivering better designer productivity and significantly improved wirelength and power. Unified implementation, timing and IR signoff engines enhance signoff convergence and reduce design margins and iterations.

To speed the design process in Samsung Foundry’s advanced-process technologies, example flows are now provided for common high-performance computing (HPC) tasks such as concurrent macro and standard cell placement, clock mesh, balanced H Tree clock distribution, power delivery network and IR optimisation.

The complete Cadence RTL-to-GDS flow optimised for the Samsung Foundry process includes the Genus Synthesis Solution, Cadence Modus DFT Software Solution, Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Tempus ECO Option, Tempus Power Integrity Solution, Voltus IC Power Integrity Solution, Conformal Equivalence Checker, Conformal Low Power, Litho Physical Analyzer and CMP Predictor.

“With the ongoing innovation in hyperscale computing and autonomous driving, there is ever-increasing demand for HPC capacity,” said Sangyun Kim, vice president of the Foundry Design Technology Team, at Samsung Electronics. “By combining the latest Samsung Foundry advanced-process nodes with the Cadence 20.1 digital full flow, our customers can achieve their design goals quickly and efficiently.”

“The newly optimised Cadence digital flow makes it much simpler for customers to achieve PPA targets using Samsung Foundry’s advanced-process technologies,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence. “By expanding upon our longstanding collaboration with Samsung Foundry, designers can rapidly adopt Samsung Foundry’s validated HPC methodologies to deliver exceptional silicon performance on time.”

Author
Neil Tyler

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