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Codasip releases first Linux-capable RISC-V core

Codasip, a supplier of customisable RISC-V embedded processor IP, has released the Bk7, the most advanced core in the Codasip family of RISC-V processor IP, and built specifically for customisation and domain-specific optimisation.

The Bk7 is intended for any sophisticated modern application, from security to real-time AI processing, especially where embedded Linux is required.

The Codasip Bk7 is a 64-bit processor core with a single in-order 7-stage pipeline, fully compliant with the RV64IMAFDC instruction set architecture (ISA). As with all Codasip Bk cores, the open RISC-V standard makes it possible to configure and extend the core to precisely fit the customer’s domain-specific needs.

RISC-V-based processors are customisable by design, but the customisability can present a challenge for chip manufacturers in terms of time-to-market. Any custom changes need to be reflected in the RTL code, the instruction set simulator and the compiler, and most importantly, the customized design must be thoroughly verified, which traditionally requires considerable time and effort.

The Codasip Studio toolset, used to design the Bk7, makes the whole process faster and easier by automating these tasks. Studio uses a single high-level description of a core written in CodAL, an easy-to-learn C-like language. Once this description is updated with any required custom changes, Studio will use it to automatically generate a complete customized HDK and SDK, including a full UVM verification environment - everything needed to deploy the core.

With Bk7, Codasip has taken this unique approach a step further by developing a new, module-based architecture for even easier CodAL editing.

The off-the-shelf configuration of Bk7 includes support for the RISC-V atomic and floating-point extensions (both single and double precision), a memory management unit (MMU), and support for privilege modes needed for richer operating systems including Linux. Bk7 also features an internal interrupt controller, dynamic branch prediction (BHT, BTB, RAS), JTAG and RISC-V debug, and standard bus interfaces (AMBA).

In-built customisable options include the branch predictor, instruction and data caches, store buffer, and others. Future releases of Bk7 will additionally include tightly coupled memories, dual issue microarchitecture, and multicore support.

The Bk7 comes in a package that contains all supporting tools to deploy the core: the CodAL description (fully editable in Codasip Studio), RTL code of the default configuration, the CodeSpace IDE to write software for the core, C compiler (LLVM and GCC), source files and compilation guide for Linux, and Linux boot demo SoC.

Author
Neil Tyler

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