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Codasip boosts Studio processor design tools

Codasip, a supplier of customisable RISC-V processor IP and tools, has announced further enhancements to its Studio processor design toolset.

New features in Studio 9.1 include an expanded bus support with full AXI for high-performance designs, as well as improved support for LLVM and improved code density.

Studio looks to simplify the task of customising designs, enabling companies of all sizes to differentiate their products at the core. Launched in 2014 Studio simplifies processor customisation and helps designers through the steps necessary to create their custom RISC-V processor from a Codasip embedded or application core design – ensuring the design achieves predictable results and the highest possible levels of performance.

Studio is part of a rapidly expanding community of RISC-V developers around the world and, with the launch of Studio 9.1, will enable higher-performance and lower cost designs.

Specifically in 9.1, Studio users gain access to additional bus interfaces, to now include full AXI which means Studio will readily support the development of more powerful application cores and multi-core systems.

Instruction memory size can dominate cost in embedded processors so code density improvements in Studio 9.1 will help to contribute to reducing overall system costs.

Codasip’s update incorporates the LLVM-based SDK (the fast C/C++ compiler, Linker Support Package – all of which were incorporated as part of Studio 9.0 launched in April 2021). This update significantly improves support for custom instructions in application cores running a rich OS, such as GNU/Linux.

Another new feature brings support for ISA sub-targets that hugely reduce the maintenance of different SDKs for different ISA configurations.

Author
Neil Tyler

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