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Cadence unveils next-generation Palladium Z2 and Protium X2 systems

Cadence Design Systems has announced the Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems that are intended to be able to handle increasing system design complexity and time-to-market pressures.

These next-generation systems have been designed to enable the highest throughput pre-silicon hardware debug and pre-silicon software validation for the industry’s largest multi-billion-gate system-on-chip (SoC) designs.

Dubbed the Cadence “dynamic duo” for its tight integration with unified compiler and interfaces, the next-generation emulation processors and Xilinx UltraScale+ VU19P FPGAs in these systems provide customers with 2X capacity and 1.5X performance improvements over their predecessors, allowing design engineers to run more validation cycles on bigger chips in less time. Additionally, both systems offer breakthrough modular compile technology capable of compiling 10 billion gates in under 10 hours on the Palladium Z2 system and in under 24 hours on the Protium X2 system.

“The complexity of our high-end graphics and hyperscale designs increases with each generation, while our time-to-market schedules tighten,” said Narendra Konda, senior director, hardware engineering at NVIDIA Corporation. “Using the common front-end flow in the Cadence Palladium Z2 and Protium X2 systems, we are optimising workload distribution between verification, validation and pre-silicon software bring-up. With twice the useable capacity, 50 percent higher throughput, and faster modular compiler turnaround, we can validate our most sophisticated GPU and SoC designs comprehensively and on schedule.”

The Palladium Z2 and Protium X2 have been developed to address the challenges faced by those designing for the most advanced applications, including mobile, consumer and hyperscale computing designs. With its seamlessly integrated flow, unified debug, common virtual and physical interfaces, and test-bench content across the systems, they are able to offer rapid design migration and testing from emulation to prototyping.

“Pre-silicon verification of advanced SoC design requires a solution with multi-billion-gate capacity that offers both highest performance and rapid predictable debug,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “Our new dynamic duo meets these requirements with two tightly integrated systems, Palladium Z2 emulation optimized for rapid predictable hardware debug and Protium X2 prototyping optimized for highest performance multi-billion-gate software validation. We are excited by the strong customer interest and look forward to partnering with them to leverage these new systems to achieve the highest verification throughput on their designs.”

Author
Neil Tyler

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