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Cache management improved

Credit: Jose-Luis Olivares/MIT

Researchers from MIT have updated the Tardis scheme – which manages memory on computer chips – from a sequential consistency standard to a more relaxed, parallel execution of instructions.

Launched last year, the Tardis scheme is claimed to use chip space more efficiently than existing memory management schemes because it coordinates cores’ memory operations according to ‘logical time’ rather than chronological time. With Tardis, every data item in a shared memory bank has its own time stamp. Each core has a counter that time stamps the operations it performs. No two cores’ counters need agree, and any given core can keep churning away on data that has since been updated in main memory, provided that the other cores treat its computations as having happened earlier in time.

The challenge posed by multicore chips is that they execute instructions in parallel, while in a traditional computer program, instructions are written in sequence. A standard chip from Intel might assign the sequence of read/write instructions ABC to a core but let it execute in the order ACB. These relaxed standards of consistency allow chips to run faster.

“Let’s say that a core performs a write operation, and the next instruction is a read,” graduate student Xiangyao Yu says. “Under sequential consistency, I have to wait for the write to finish. If I don’t find the data in my cache, I have to go to the central place that manages the ownership of data.”

“This may take a lot of messages on the network,” he continues. “And depending on whether another core is holding the data, you might need to contact that core. But what about the following read? That instruction is sitting there, and it cannot be processed. If you allow this reordering, then while this write is outstanding, I can read the next instruction. And you may have a lot of such instructions, and all of them can be executed.”

To enable Tardis to accommodate more relaxed consistency standards, the researchers gave each core two counters, one for read operations and one for write operations. If the core chooses to execute a read before the preceding write is complete, it gives it a lower time stamp, and the chip as a whole knows how to interpret the sequence of events.

The Tardis will therefore supposedly offer a unified framework for managing memory at the core level, at the level of the computer network, and at the levels in between.

Author
Peggy Lee

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