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Arasan announces MIPI Soundwire IP solution

Arasan Chip Systems, a provider of semiconductor IP for IoT, mobile and automobile SoC's has announced the immediate availability of its MIPI Soundwire PHY I/O IP.

As a consequence, Arasan is now able to provide a Total IP solution for MIPI Soundwire in compliance with the latest Soundwire Specifications v1.2

MIPI SoundWire protocol is a simple, unified audio interface that has evolved to numerous markets, especially mobile applications to replace several high pin-count connections, allowing for greater scalability and flexibility, improved power consumption, and decreased latency.

MIPI SoundWire is suitable for a wide range of devices such as personal computers, high-end mobile phones, headphones, and hearing aids, ranging from low-cost, low-bandwidth peripherals to high-performance audio codec.

Arasan's Soundwire Phy v1.2 comprises PHY Host IP with 1 clock lane, 1 data lane and PHY Device IP with 1 clock lane, 3 data lanes. It has been designed to seamlessly integrate with Arasan's Soundwire Host and Device Controller. Arasan's Soundwire PHY features a programmable delay for high-Z to driving data timing and for accommodation of time to enable Data output signal edge on Clock input, capability for both synchronous and self-timed turn off data output, one-shot with programmable pulse width for self-timed turn off data output. It supports 1.8V +/-10% supply for IOs and 0.8V +/-10% supply for core.

The Soundwire PHY I/O IP is silicon proven and is now available for FinFET process nodes.

Author
Neil Tyler

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