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John Isaac, director of market development, Mentor Graphics

Graham Pitcher talks with John Isaac, director of market development for Mentor Graphics' systems design division.

A survey by Prismark published in August 2009 took a look at what electronics oems were investing in. No surprise to find out that all were investing in new product development, but it may be more interesting to find out that more than 70% were investing in process development.
John Isaac, director of market development for Mentor Graphics' systems design division, has been around long enough to know that what goes around comes around. And he sees industry well into recovery from the effects of the global recession.
Isaac believes that companies get stronger by investing during downturns and one aspect of process development is investing in advanced design technologies. "But it is important to know when to use this technology and – importantly – how to use it," Isaac observed.
The need for advanced design technologies is highlighted by analysis of entries to Mentor Graphics' annual PCB Technology Leadership Awards (TLA), which were established in 1988. This programme recognises the engineers and designers who use innovative methods and design tools to address complex pcb systems design challenges and who produce industry leading products.
Entries to last year's competition highlight some interesting statistics.
The entries showed that trace spacings are now, on average, 4mil and boards have, on average, 14 metal layers. This contrasts to 1994, when trace spacing was 6.5mil and boards had eight metal layers. Where an average board was 101sq in in 1994, today's board is only 75sq in.
But the big difference is found when you look at the number of nets, pin to pin connections and components. The latest values are 3411 (1465 in 1994), 10,960 (5190) and 3399 (649) respectively.
Here's some figures from the 2009 TLA which will help you to put your designs in perspective.
Biggest board: 490 × 368mm
Smallest board: 12.5 × 10.6mm
Most layers: 32
Average trace/space: 100 × 100µm
Most vias: 73,847
Most nets: 13,178
Most connections: 55,982
Most components: 22,236
Most FPGAs: 48
Isaac cites, as an example, an entry into the TLA from Qualcomm. The board features 32 layers and 26,270 connections, with 65% of the components running at high speed. "The design made a lot of use of autorouting," Isaac observed. "Autorouting isn't always looked on favourably by pcb designers; they think they can do a better job. But Qualcomm has used it successfully."
Isaac said autorouting is typically used to run through a number of scenarios asking such questions as 'will it route?' and 'can I meet the constraints?'.
"Qualcomm used Xtreme AR (Mentor's autorouting technology) to support up to 15 processors on the same board, but designers could still route critical nets manually. Two years ago, IBM said it would never have finished one of its designs because it had to run too many experiments. It honed in on the solution when it turned to Xtreme AR."
Amongst some of the comments from IBM were 'we wouldn't have hit the market window' and 'better never than late'.
Prismark's survey predicts the use of microvias will grow more quickly than other technology aspects. "But just because it has an advantage, it doesn't mean it's always applicable," Isaac cautioned. "The design needs to be analysed to see if high density interconnect (HDI) is stable."
But it can bring big benefits. "A 16 layer through hole design can be turned into a 12 layer board featuring HDI. And through hole designs can create current traps; HDI avoids this, while bringing better signal integrity."
Another metric which Mentor found from analysing its TLA entries was the number of pins per sq in. Today, the average is 398, but some designs are well in excess of this. "The industry is moving, in some cases, towards 2000pins/sq in – one design submitted to TLA featured 1820pin/sq in using flip chip on board technology.
More pins brings higher routing densities. Mentor has developed technology that copes with HDI. "It allows you to define regions of a bga and a fanout strategy through microvias to lower levels," Isaac noted. "Then, using breakout routing, you can move from the microvia pads in one of two ways: you can use the traditional north, east, south, west approach, or you can just go in the direction the trace needs to go. This allows designers to do this in a minute or two; it would have taken days by hand."

www.mentor.com
communities.mentor.com

Author
Graham Pitcher

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