Silicon success for Graphcore's multi-billion gate AI processor

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Synopsys has announced that Graphcore has achieved first-pass silicon success with its second-generation Colossus MK2 GC200 Intelligence Processing Unit (IPU), featuring 59.4 billion transistors, on an industry-leading 7nm advanced process technology.

This was achieved by using Synopsys' IC Compiler II place-and-route solution, part of its Fusion Platform.

Graphcore said that it had been able to leverage the IC Compiler II's ultra-high capacity architecture and technologies for AI-hardware design resulting in an accelerated implementation of their massive AI processor. Synopsys' RTL-to-GDS flow with state-of-the-art power optimisation capabilities along with embedded golden signoff technologies like PrimeTime delay calculator, provided Graphcore's design teams with out-of-the-box PPA metrics, and much faster design closure.

"Synopsys's digital full-flow solution, including Design Compiler and IC Compiler II, offers a comprehensive single-vendor platform, critical to the on-schedule tape out of our latest Colossus IPU," said Phil Horsfield, vice president of Silicon at Graphcore. "Our long-standing relationship with Synopsys has enabled us to leverage state-of-the-art technologies from IC Compiler II and exceed the performance/power targets of this advanced AI processor. Continued collaboration with Synopsys on IC Compiler II and Fusion Compiler will enable us to push the boundaries of machine intelligence compute even further."

Graphcore's Colossus GC200 IPU is an extremely sophisticated chip, integrating 1,472 independent processor cores and more than 900 megabytes of on-chip memory to deliver parallel processing power for data-centre scale AI applications.

Synopsys' IC Compiler II, with its AI-design focused capabilities, includes top-level interconnect planning, logic restructuring, congestion-driven mux optimisation and full-flow concurrent clock and data optimisation is able to deliver best-in-class PPA for the highly repetitive, MAC-based topologies typical in complex AI accelerator chips. Further, its native, high-capacity data model with adaptive abstraction and distributed implementation can efficiently handle multi-billion instance designs with quick turn-around-time. With a unique, golden signoff engine backbone, IC Compiler II is able to deliver correlation and hyper-convergent design, helping to accelerate design turnaround time.

"The design complexity boundaries of AI compute are continuing to be pushed to its limits, such as with Graphcore's introduction of its latest Colossus IPU," said Neeraj Kaul, vice president of Engineering, Design Group at Synopsys. "Its success in leveraging the latest, AI-optimised technologies in IC Compiler II to simultaneously meet the multiple aggressive design targets for their most complex chip reinforces our leadership position as the place-and-route tool of choice for next-generation, AI designs."