The solutions integrate CAST’s validated design IP for both standards with Avery’s verification IP (VIP) that streamlines the design and verification process as well as compliance with the standards. The new solutions include the CAN XL and TSN Ethernet design IP from CAST and the corresponding VIP from Avery.
CAN XL is the third generation of the CAN data link layer that enables net data rates of up to 10Mbit/s and supports an extra-large (XL) payload of up to 2048 bytes. High speed Ethernet in automotive supports the need for multiple streams of data from cameras, sensors, and radars to be transferred and processed in real time. Time Sensitive Networking (TSN) addresses the scheduling, low-latency, and safety requirements of mission-critical control systems like braking, steering, ADAS and other functions.
The expanded partnership builds on the companies’ existing relationship and creates best-in-class, robust, pre-validated CAN FD/XL and TSN Ethernet MAC solutions, streamlining the design and verification process for mutual customers.
Avery’s virtual prototype solution for CAN XL and TSN Ethernet enables running CAST’s CAN XL IP and TSN Ethernet MAC reference designs and software stack in a QEMU/SystemVerilog co-simulation solution running on RTOS and supports RISC-V, Arm, and Microblaze embedded processor solutions.
“As an increasing amount of data gets moved throughout and around the connected automobile chip developers need the latest high-bandwidth and high-speed connectivity solutions enabled by evolving networking standards. CAST has a long track record of providing reliable and accurate IP solutions to incorporate the latest automotive networking functionality in SoCs, and this expands our established partnership to deliver high quality VIP to further accelerate the verification of these designs,” said Chris Browy vice president of sales and marketing at Avery.
Avery’s VIP can be used by designers to ensure complete verification of their designs and full protocol and timing compliance. The solution includes a ready-to-use set of models, protocol checkers, and compliance testsuites in 100% native SystemVerilog and UVM.