Affordable fpga based asic/SoC prototyping

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Paris based Reflex CES has partnered with fpga design partitioning software specialist Flexras and functional verification software provider Adacsys to develop a validation and verification platform for asics and SoCs.

Aimed at emulating designs with up to 25million asic gates, the FPP25 system is based on Xilinx Virtex-7 2000T fpgas. Up to five FPP25 boards can be daisychained to support designs with up to 125million asic gates. Reflex CES started as a custom designer of high performance pcbs for embedded systems, focusing on high speed applications incorporating high end fpgas and SoCs. Flexras was an early customer, requiring an asic prototyping platform to demonstrate its Wasga Compiler Design Suite partitioning software for accelerated SoC prototyping. The latest version, Wasga 3.2, is claimed to be the only timing driven partitioning tool for SoC rapid prototyping that partitions large designs automatically on to multiple fpgas, while addressing chip resources, connectivity and the clock frequency constraints required for running software in near real time. Wasga is a generic solution that can be configured for use with commercially available or in house hardware prototyping systems. Meanwhile, Reflex's mainstream business has shifted from full custom boards towards more standard functionality with some modifications. Jacques Figeiredo, sales engineer, said: "Modifications may be as simple as a different or additional interface, but may also be replacing the cpu with an SoC." Coincidentally, Reflex has seen interest grow in fpga based SoC prototyping systems. The FPP25 platform, which features Flexras' partitioning software, is an obvious outcome as part of Reflex's modified off the shelf product strategy. The Adacsys AVA Advanced Verification Acceleration software can be added as an option. A spin off from Mentor Graphics see NE, 11 December 2012, Adacsys, which specialises in low cost fpga based verification and debug of high performance embedded systems, says its solution is complementary to the full hardware emulation approach, providing a simpler means of early verification.