The challenges are myriad, but new methods are emerging to take advantage of the third dimension that promise not only to overcome the challenges but to deliver new and vital functionality to the systems-on-chip (SoC) that will power the Internet of Things (IoT).
The slowing of silicon scaling (or, as some might say, the economic punishment that continued silicon scaling brings) has sparked a number of creative alternatives. Prime among these is the move to go vertical with silicon designs – to stack SoCs to take advantage of that vertical dimension. This has been seen most broadly and effectively in 2.5D and 3D chip stacking.
Chip stacking helps the systems deliver on the promise of Moore’s Law even as the classic Moore’s Law method, feature-size reduction in the transistors, has begun to slow. But it’s also delivering an enormously vital new function for IoT systems: Heterogeneity. IoT devices are required to perform a range of different functions. These range from analog sensing and energy-harvesting to digital processing and wireless communication, all within very strict power and volume constraints. To manage this, it is common that integration of these different components happens within the chip. Often, however, each component prefers its own silicon process technology, so combining these different elements is not a straightforward task.
There are three classes of 3D, ranging from stacking chips together more efficiently to building stacked transistor patterns effectively within an IC. Each has its own benefits and challenges:
- 3D stacked IC (SIC)
- 3D SoC
- 3D IC
The 3D stacked IC includes a variety of technologies, but they all use semiconductor technology in some way that improves die-to-die interconnect beyond what conventional packaging can provide. The 3D-SIC is different than decades-old multi-chip module (MCM) technologies in that they achieve much higher interconnect densities with the use of a defining technology: the through-silicon via (TSV) to connect the various levels.
DRAMs were the first semiconductors to exploit the benefits of 3D SIC technology. Existing memory interfaces were becoming hamstrung by traditional packaging interconnect density, eventually pushing to the limits of packaged pin count and frequency. By stacking DRAM slices in true 3D form, and utilizing TSV technology to enable a much “wider” I/O, Micron (Hybrid Memory Cube, 2013) and Hynix (High-Bandwidth Memory, 2015) began shipping products that could far out-perform the conventional packaging’s access to DRAM.
But it was at the 2017 International Electron Devices Meeting (IEDM) where things got interesting. There, AMD discussed how they utilized 2.5D (with 3D-SIC DRAMs) to get the power efficiency gains in a GPU. They also discussed how they partitioned their 32-core EPYC server-class chip to four 8-core “chiplets”, connected with their proprietary on-package interconnect. Even with a 10% overhead to add I/O to the 4 chiplets, AMD was able to reduce their overall cost on the order of 41% thanks to improved yield (yield being an exponential function of chip area).
In a short amount of time, 3D SICs have gone from lab demonstrators to real products showing significant advantages in cost and performance. These 3D-SIC solutions will improve power and performance over what basic transistor scaling can provide us, and can ultimately lower costs as well.
'Stacked IC' technologies are beginning to provide significant advancements in power and performance for end systems. But, for the most part, the TSV pitches in the few 10s of microns limit partitioning at the 'chiplet' level, meaning that we need to limit our 3D architectures to things that can be partitioned using somewhat conventional I/O protocols. But now that TSV-based technology is delivering real results to real systems, we can expect the technology to drive toward increasingly finer pitches. And if/when they get to around 1-2um in pitch, they could support partitioning at levels inside the SoC, realizing 3D “system on chip” (3D-SoC) partitioning.
One technology that can deliver 3D SoC benefits in the short term is wafer-level bonding, as opposed to the chip-level stacking that we’ve discussed so far. Stacking wafers can be ultimately cheaper than stacking chips, but wafer-level bonding also brings also wafer-alignment technology that far surpasses the accuracy discrete chip placement.
Discrete chip placement accuracy will improve, and ultimately we should expect to be able to implement 3D SoC with chips. This will open up a wide space of potential benefits. A 2017 Nature article by Stanford researchers described one example of heterogeneous, chip-level 3D SoC providing revolutionary improvements to system efficiency. Relevant to the IoT, the top layer of this system was a sensor layer, and the rest of the system implemented ML to identify sensor signals.
That 3D approach used carbon nanotubes (sheets of 2-D graphene formed into cylinders) and integrated resistive random-access memory (RRAM) cells. The Stanford researchers integrated more than 1 million RRAM cells and 2 million carbon-nanotube field-effect transistors (CNT FETs) in the chip. Instead of requiring separate components, the RRAM cells and carbon nanotubes were built vertically over one another, which allowed for a dense inter-weaving of logic and memory functionality.
One does not need CNT FETs and novel RRAM to benefit from 3D SoC. However the Stanford design showcases how 3D SoC enables radical departures from the tyranny of CMOS process compatibility, allowing incompatible technologies to be interconnected intimately enough to operate as if they were monolithic. The novel architecture sat on a fourth layer, a standard CMOS chip that provides the normal interface(s) to the outside world, demonstrating that in the future value may not only come from what you do to CMOS, but also what you put on top of it. Examples you might expect to see in the future range from non-silicon-based high mobility MOSFETs to novel photonic devices.
The final, and finest, version of 3D is transistor-level 3D. Transistor-level 3D is more of a straight-on attack at furthering Moore’s Law. As such, it has the potential deliver continued cost and power benefits, as we’ve been accustomed to receiving from process node advances.
There are several ways to stack transistors. One possible path follows somewhat naturally from the transistor scaling plan of record, which sees the industry “pivoting” gracefully from the FinFET to a new device called 'gate all-around' (GAA) FET (also called a horizontal nanowire or nanosheet FET).
The GAA-FET requires multiple transistor channels to be suspended and stacked on top of one another. With that capability in hand (probably by the 3nm or 2nm node), it is logical to further advance transistor density with what is labelled 'CFET', or 'complimentary FET', which is a stacking of not just N or P channels to make a GAA FET but stacking N channels over P channels to effectively place an inverter in the space formerly occupied by a single transistor. If we can pull off the CFET, we may then figure out how to make more than two layers of N/P FETs, and push transistor density even further without having to rely solely on pitch reduction, realizing long-term 3D IC benefits.
As we explore these paths, we will run into some design headwinds, notably already burdensome parasitic resistance and capacitance found in nanometer transistors. There will also be thermal issues to consider. Offsetting these headwinds are likely additional benefits that will come from utilizing this ultimate connection density in modified chip architectures and microarchitectures.
For future semiconductor technologies, the system design challenges are extraordinary, as engineers ponder how to deliver the best efficiency, cost and size they can with their system designs. As conventional scaling approaches strain these visions, new methods for vertical scaling at the transistor, chip and system level offer enormous promise to help propel us into a new era of design innovation.
Author details: Greg Yeric is a Fellow with Arm, whose research delves into efforts to leverage new device and materials innovations to help the industry deliver better components