EDA & Design Software

Synopsys gives a boost to 5G SoC development with new RF design flow

QuickLogic and eTopus develop flexible eFPGA chiplet template

Alchip Technologies offering 3nm ASIC design services

Siemens extends support of multiple IC design solutions for TSMC’s latest processes

Avery Design Systems announces verification support for new UCIe standard

Cadence Design IP portfolio in TSMC’s N5 Process gains broad adoption

SkyWater announces availability of 90nm SRAM memory compiler

OpenLight launches silicon photonics technology platform

Cadence accelerates SoC verification with expanded VIP and System VIP portfolio

FPGA Retargeting: The Why, What and How

Siemens streamlines and secures embedded RISC-V development

Cadence partners with McLaren Racing