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Universal DDR Controllers for embedded DRAM interfaces

Synopsys has announced the DesignWare Universal DDR Protocol and Memory Controllers, which it says offers improved performance and reduced cost of embedded DRAM interfaces.

Both controllers are said to support the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards, deliver memory system performance of up to 2133 Mbps, and offer a broadly utilised DFI 2.1 compliant interface to the DDR PHY.

According to Synopsys, the memory controller helps reduce both the latency and silicon area by up to 50% compared to Synopsys' previous generations of DDR memory controllers, improving the DRAM interface performance and reducing overall chip costs. It has been designed to provide efficient DDR control and protocol translation for applications, without the need for a multi ported memory controller.

The controllers are said to enable designers to easily integrate multiple DDR interfaces into one design with less risk and improved time to market. The DDR Memory Controller reportedly accepts memory access requests from up to 32 application side host ports, each of which can be configured independently to be synchronous or asynchronous to the controller clock.

Author
Laura Hopperton

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