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Improving product creation time with PCB design and analysis methodology for multi-gigabit interfaces

Cadence Design Systems has announced the availability of the Sigrity 2016 technology portfolio, which is claimed to improve product creation time with an enhanced PCB design and analysis methodology that is suitable for multi-gigabit interfaces.

To speed the qualification of a physical design for the USB Implementers Forum compliance test, the Cadence Sigrity technology portfolio includes automated support for IBIS-AMI model creation, channel model extraction using multiple field solvers, and an automated power-aware signal integrity analysis report to validate a virtual USB 3.1 channel. Cadence says that weeks can be shaved off the design process when these technologies are used together.

The Sigrity 2016 technology portfolio uses validated equalisation algorithms used by the Cadence Design IP SerDes PHY team and is said to provide an automated methodology for combining, paramaterising and compiling the algorithms into an executable model.

‘Cut and stitch’ technology makes the creation of accurate channel models ten times faster by using a mix of hybrid and 3D full-wave field solvers. With minimal manual intervention, the serial link channel can be divided into sections, solved for and automatically stitched together into a single interconnect model.

Tom Austin-Morgan

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