10 December 2009 System Verilog & OVM: Mitigating verification challenges and maximising resusability This white paper from Applied Micro looks at the challenge of verification – a nightmare for engineers with the increasing requirements and complexity of the design – and mitigating the complexity of a verification environment with the increasing complexity of design verification. System Verilog, along with its library of classes – OVM, provides a platform to face this challenge. Author Parag Goel and Pushkar Naik Related Downloads 21087\AppliedMicro.pdf Comment on this article Websites http://www.appliedmicro.com Companies Applied Micro Circuits (AMCC) UK Ltd This material is protected by Findlay Media copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team. Enjoy this story? People who read this article also read... NIDays 2013 NIDays is a technical conference designed specifically for ... Read Article Southern Manufacturing This year, Southern Manufacturing and Electronics is set to be ... Read Article USB implementation simplified In a move aimed at simplifying isolated USB port implementation ... Read Article Claire Jeffreys, NEW Claire Jeffreys, events director, National Electronics Week, ... Read Article What you think about this article: Add your comments Name Email Comments Your comments/feedback may be edited prior to publishing. Not all entries will be published. Please view our Terms and Conditions before leaving a comment.