comment on this article

High speed board layout challenges in fpga/sdi subsystems

This white paper from National Semiconductor outlines the layout challenges facing hardware engineers when working in fpga/sdi subsystems and provides recommendations for dealing with these challenges.

Author
Tsun-Kit Chin, applications engineer, National Semiconductor

Related Downloads
20849\National Semiconductor_Technology Edge.pdf

Comment on this article


This material is protected by MA Business copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team.

What you think about this article:


Add your comments

Name
 
Email
 
Comments
 

Your comments/feedback may be edited prior to publishing. Not all entries will be published.
Please view our Terms and Conditions before leaving a comment.

Related Articles

LoRa evaluation kits

Microchip has launched what it says are the industry’s first complete LoRa ...

Thinner but brighter

In today’s wearable health and fitness market, where consumer electronic ...

Hardware development

In today’s fast-paced, connected world, the need for more capable and adaptable ...

Interesting times

It has certainly been an interesting year for chip giant Qualcomm. Revenues are ...