20 November 2009 High speed board layout challenges in fpga/sdi subsystems This white paper from National Semiconductor outlines the layout challenges facing hardware engineers when working in fpga/sdi subsystems and provides recommendations for dealing with these challenges. Author Tsun-Kit Chin, applications engineer, National Semiconductor Related Downloads 20849\National Semiconductor_Technology Edge.pdf Comment on this article Websites http://www.national.com Companies National Semiconductor Corp This material is protected by Findlay Media copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team. Enjoy this story? People who read this article also read... NIDays 2013 NIDays is a technical conference designed specifically for ... Read Article Southern Manufacturing This year, Southern Manufacturing and Electronics is set to be ... Read Article Arrow buys Nu Horizons Arrow is buying Nu Horizons in an all cash deal which values the ... Read Article Claire Jeffreys, NEW Claire Jeffreys, events director, National Electronics Week, ... Read Article What you think about this article: Add your comments Name Email Comments Your comments/feedback may be edited prior to publishing. Not all entries will be published. Please view our Terms and Conditions before leaving a comment.