20 November 2009 High speed board layout challenges in fpga/sdi subsystems This white paper from National Semiconductor outlines the layout challenges facing hardware engineers when working in fpga/sdi subsystems and provides recommendations for dealing with these challenges. Author Tsun-Kit Chin, applications engineer, National Semiconductor Related Downloads 20849\National Semiconductor_Technology Edge.pdf Comment on this article Websites http://www.national.com Companies National Semiconductor Corp This material is protected by MA Business copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team. Enjoy this story? People who read this article also read... Alternative back-up power With outdoor events like concerts, events and festivals now ... Read Article NIDays 2013 NIDays is a technical conference designed specifically for ... Read Article Southern Manufacturing This year, Southern Manufacturing and Electronics is set to be ... Read Article Remotely access up to 16 ... Lantronix is set to launch its latest evolution device/terminal ... Read Article What you think about this article: Add your comments Name Email Comments Your comments/feedback may be edited prior to publishing. Not all entries will be published. Please view our Terms and Conditions before leaving a comment.