comment on this article

High speed board layout challenges in fpga/sdi subsystems

This white paper from National Semiconductor outlines the layout challenges facing hardware engineers when working in fpga/sdi subsystems and provides recommendations for dealing with these challenges.

Author
Tsun-Kit Chin, applications engineer, National Semiconductor

Related Downloads
20849\National Semiconductor_Technology Edge.pdf

Comment on this article


This material is protected by Findlay Media copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team.

Enjoy this story? People who read this article also read...

What you think about this article:


Add your comments

Name
 
Email
 
Comments
 

Your comments/feedback may be edited prior to publishing. Not all entries will be published.
Please view our Terms and Conditions before leaving a comment.

Related Articles

The X-Gene factor

In 2010, Applied Micro made a strategic decision; courageous or foolhardy, ...

Fibre optic modules

Four new devices have been added to Toshiba's TOSLINK family of fibre optic ...

A question of logic

One of the advantages of the programmable logic device is its ability to be ...

Jamie Urquhart

Jamie Urquhart tells Graham Pitcher the time is right for the UK's electronic ...