14 December 2010
DSP core and memory architecture improvements: KeyStone multicore architecture for C66x DSPs
In a multicore SoC environment, memory efficiency is crucial for the system performance. TI's KeyStone architecture offers a highly memory efficient architecture, which is critical for multicore system performance with improvements to the cache, shared memory, and external memory interface architectures.
KeyStone includes TI's newest TMS320CC66x DSP core, which supports both fixed-point and floating-point operations. It doubles the data paths within the CPU functional units and cross-paths. It also quadruples the available SIMD data widths for operations from the register files to allow 128-bit (quad-32-bit) values. With upgraded instruction sets, the C66x DSP core is optimized for complex arithmetic and linear algebra and provides 4 times MAC capability over existing solutions. At the same time, it provides full binary compatibility with TI's C64x+ and C674x+ DSPs.
Learn more about C66x Multicore DSPs
Author
Chris Shaw
Supporting Information
Websites
http://focus.ti.com/dsp/docs/dspcontent.tsp?contentId=77428
http://www.ti.com/ww/eu/
Companies
Texas Instruments
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