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Working to the clock


Driving jitter in serial architectures to new low levels. By Graham Pitcher.

Originally developed for desktop and server applications, the Peripheral Component Interconnect, or PCI, architecture has since found application in embedded systems and communications products.
The parallel bus architecture has evolved into a number of variants, one of the latest being PCI Express. This has been developed to address the current and future system interconnect requirements of various market segments. PCI Express – originally promoted by an industry group led by Intel and known as 3GIO – provides a high speed, serial point to point interconnect that is flexible and scalable.
High speed networking technologies such as PCI Express – but also Gigabit Ethernet and Fibre Channel – require high frequency oscillators for their reference clocks. John Greyerbiehl, a product marketing engineer with Epson Electronics Europe (http://www.epson-electronics.de), said: “The reference clock is one of the most critical aspects of the design, since it is used as input to a transceiver containing a PLL (x10 or x20) to generate much higher frequencies for transmitting and receiving data rates exceeding 1Gbit/s. It is therefore critical that the reference clock has low levels of jitter.”

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Vanessa Knivett

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