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FRAM set to save energy in write intensive mcu applications

  • TI has launched a series of 16bit mcus with fram
  • Peter Peisker, mcu business manager for TI EMEA

Texas Instruments has launched the first of a series of 16bit microcontrollers that use ferroelectric memory (fram) instead of flash, claiming that the combination will save energy in low duty cycle, write intensive applications such as smart meters.

Matthias Poppel, embedded processing marketing director for TI EMEA, said writes to fram can use 250 times less energy than writes to flash. However, the memory technology, which first appeared more than 20 years ago, has proven difficult to put into production. The only other company with embedded fram microcontrollers is Fujitsu, which launched an 8bit family last year.
The MSP430FR57 family of microcontrollers, which currently provides up to 16kbit of on chip fram, is partly the result of a joint development programme with Ramtron signed almost ten years ago. TI is currently sole foundry for the fram specialist: arrangements to use IBM as a second source have been hit by delays.
"In terms of manufacturing, we now have a very stable process," said Peter Peisker, pictured, mcu business manager for TI EMEA, adding that, having spent some years to achieve manufacturing yields, it is now a simpler process to add fram to cmos products than it is to add flash. "We can implement fram with just two additional layers."
Manufactured in a way similar to magnetic ram devices, the cmos transistors are completed first. Then the fram capacitors – which use comparatively exotic materials that are not compatible with cmos processing, such as iridium and lead zirconium titanate – are deposited in the interconnect layers above.
TI is manufacturing its fram mcus on a 130nm cmos process. Poppel claimed that older processes, such as 0.35µm, would not have provided a sufficiently small memory cell to be economic. "The flash cell is much smaller," he said, adding the trade off is much closer at 130nm and smaller geometries, particularly with smaller arrays, because of the extra area consumed by the charge pump that is needed to program flash cells.
"The economic borderline is between 128 and 256kbit," said Poppel. "Where you need more than 512kbit, flash is still the more dense and cost effective technology. However, when we move to 90nm or 65nm processes, that will change."
One issue with using fram in high speed mcus is its read-cycle endurance, although its write endurance is far higher than that of flash. Like dram, the read is destructive if the memory cell contains a logic '1'. Because this value needs to be rewritten, reads tend to contribute far more to cell wear out than writes if code is stored in fram. TI has tested its embedded fram array to 1014 write cycles – which could, potentially, see a cell wear out in three years if read continuously at a rate of 1MHz.
Poppel claimed real world endurance could be higher: "Some studies have achieved 1016. Also, in these devices, you don't have duty cycles of 100%."
Poppel said the target for MSP430 devices is in low duty cycle environments, where the device will sleep much of the time, only waking up to take and store sensor readings. "We made some calculations and came up with a lifetime of 80 years," he said.
TI has taken the precaution of adding a small sram array that can act as a cache – the 50ns access time cannot support the full processor clock speed of 24MHz – as well as an module for correcting single bit errors.
Peisker said the fram technology provides TI with manufacturing flexibility. "It's a simpler process than flash. Manufacturing is 100% in house today, but we could transfer the process to a foundry, although there are no plans to so."
TI is, however, unlikely to mix flash with fram on larger parts – because the power needed to support flash would be too high. "I would rather put money into developing a smaller fram cell than put money into combining flash with fram," Poppel concluded.

Author
Chris Edwards

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