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Think outside the box

Of three new PCI specifications, one will take the interconnect technology truly outside the box. By Vanessa Knivett.

The PCI development community is going through a major transition. During the past decade, PCI has been a successful, general purpose I/O interconnect standard. However, emerging computing models are placing bandwidth demands and scalability limits that multidrop, parallel bus implementations such as PCI 2.2 and PCI X will not support readily.

Amongst technologies demanding greater internal bandwidth are high speed cpus, faster memories, higher speed graphics, 1G and 10Gbit/s lans, IEEE1394b and InfiniBand. It is generally recognised that a new generation of PCI is needed to serve as a standard I/O bus for next generation platforms.

Hence, three new PCI specifications have been released, PCI Express, PCI X 2.0 and PCI 2.3. Of these, PCI Express has gained the highest profile for its Gigahertz communications capabilities and completely new I/O approach. It uses a pair of differential low voltage signals to transmit data and a second differential pair to receive. Both run at 2.5Gbits/s and deliver data at 100Mbyte/s per pin.

PCI Express, in development at Intel for the last 10 years or so and formerly known as 3GIO, has been adopted as an open specification by the PCI SIG – an industry wide organisation which promotes PCI and its derivatives.

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Graham Pitcher

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