08 August 2006
The right gear
Bit based dynamic alignment for multi gigabit parallel I/O. By Shakeel Peera.
Whilst I/O standards continue to evolve towards serialisation in backplane and, more recently, chip to chip applications, high speed parallel I/O still has an important role to play where serial technologies are cost prohibitive.
Apart from established source synchronous I/O standards – such as SPI4.2, SFI4.1, XGMII, HyperTransport, Rapid IO and CSIX – the next generation of clock forwarded interfaces is being implemented on sram and dram (DDR1/2/3, RLDRAM1/2 and QDR2), and in a/d and d/a converters. The I/O speeds required for these next generation applications are expected to exceed 1Gbit/s.
FPGAs are being increasingly used as programmable SoCs, designed as an integral part of the system data path. However, the expectation is these devices can perform high speed I/O translation and processing. And users expect them to comply with past, existing and emerging I/O standards.
Although electrical compliance and high speed signal integrity are required features, these alone do not address the bandwidth issue. The fpga I/O must also have circuitry to manage and maintain the clock and data relationships of these high speed signals, as well as providing the necessary ‘gearbox’ functionality to support the transfer of high speed I/O data to the fpga fabric to perform the required processing.
Author
Shakeel Peera
Supporting Information
Downloads
6724\The-right-gear.pdf
Websites
http://www.latticesemi.com
Companies
Lattice Semiconductor UK Ltd
This material is protected by Findlay Media copyright
See Terms
and Conditions.
One-off usage is permitted but bulk copying is not.
For multiple copies contact the
sales team.