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The next memory revolution?

QDR II creates a high bandwidth sram architecture. By Kannan Srinivasagam and David Mahashin.

Demand for high bandwidth memory is growing rapidly and current memory standards are becoming bottlenecks to high speed (data rates of more than 200MHz) network routers, hubs and switches, where high bandwidth memory is a requirement. Quad Data Rate (QDR) synchronous pipelined burst sram has been designed to specifically address these needs, increasing system memory bandwidth while serving as the memory solution for lookup tables, linked lists and controller buffer memory in high performance networking systems.

QDR sram technology has been defined jointly by Cypress, IDT, NEC, Renesas, and Samsung and the latest architectural development from the collaboration is QDRII. The QDRII architecture builds upon the original QDR, providing higher bandwidth and simplifying data transfer at very high operating frequencies.

The main differences between QDRII and QDR are an added DLL, additional half cycle latency (equating to one cycle on original QDR and 1.5 cycles on QDRII). As a result, the clock to Data Valid has been reduced from 3 to 0.45ns at 167MHz. The net result is a larger data valid window, which improves system timings.

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Author
Graham Pitcher

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