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The capacity for change

Research by UK universities into ferroelectric films could bring new life to single core microprocessors

Since the late 1960s, the semiconductor industry has been propelled by Moore's Law and companies have focused on doubling the number of transistors on a given area of silicon every 18 months.

As cmos processes move towards the 16 and 11nm technology nodes, device designers are encountering significant problems. Because of these physical challenges, the focus is shifting away from scaling (or 'more Moore') towards increasing functionality through the introduction of mixed technologies on silicon (or 'more than Moore').

Work at Newcastle University, being undertaken in association with Imperial College, is investigating the incorporation of ultra thin ferroelectric materials into silicon nanoelectronics and two potential applications. The project is called FERN: ferroelectronics for nanoelectronics.

Leading the work at Newcastle is Professor Anthony O'Neill, Siemens Professor of microelectronics, with one of the avenues of research being the seemingly impossible concept of negative capacitance. "Recently," he noted, "there has been experimental evidence that effective negative capacitance can be seen in ultra thin ferroelectric films. If such material could be incorporated into a transistor, then it would be able to reduce the voltage needed to switch a transistor between its on and off states (the sub threshold slope). This would transform silicon technology, allowing for example a new generation of more powerful single core processors."

Prof O'Neill noted he wasn't the first to think about using negative capacitance. "But it hasn't been demonstrated and, even if you can show it, you have to get it to the point where it can be manufactured."

The FERN project believes negative capacitance could be applied in the gate stack of transistors. "It's an exciting option," Prof O'Neill believes.

If successful, the work is likely to address the problems with heat generated by single core microprocessors running at high clock rates. Broadly, companies such as Intel have had to move to multicore processors to keep the heat generated down to reasonable levels. However, if the sub threshold slope can be adjusted, there exists the possibility that microprocessor developers could return to the single core approach.

"Capacitance places a minimum slope for the sub threshold voltage of 60mV/decade," Prof O'Neill pointed out. "That means transistors need a larger applied voltage to be on or the leakage current is too high, or both. That means transistors are never really 'off'. If the sub threshold voltage slope can be reduced to less than 60mV/decade, developers can revisit some of the design roadblocks."

Integrating a ferroelectric film with negative capacitance into the gate of a transistor would reduce the overall capacitance and thus the sub threshold swing.

But what is negative capacitance and how can it be achieved? Prof O'Neill said that it arises from a positive feedback in ferroelectrics, which is stabilised by putting it in series with the gate capacitance. So the approach is more about reducing the capacitance of the overall gate stack. "It provides a step up voltage transformer," he added.

He accepts there are other ways to address the problem, including tunnelling and avalanche breakdown, but said that he doesn't see how the latter approach could be controlled.

Capacitance is, of course, the rate of change of charge with voltage. Because their electric permittivity is so high, ferroelectrics also hold the potential to shrink capacitors in size by three orders of magnitude. "More than that," said Prof O'Neill, "their capacitance can be made to vary depending on the applied voltage, allowing the potential for very small, tuneable capacitors to be made on chip."

However, to use ferroelectrics late in a silicon process would require temperatures to be kept less than 500°C in order to avoid phase changes. "We therefore plan to deposit material using the low temperature process of atomic layer deposition (ALD). It's an opportunity because a capacitor could be built in a smaller area and which could be tuneable using an electric field."

Major funding has been provided by CPI and the EPSRC. CPI is embedded at Newcastle University and shares a cluster tool for ALD and sputter deposition in clean rooms gifted to the university by CPI. Alongside Newcastle and Imperial, the FERN project is also being supported by Intel Ireland, which is sponsoring a research student, and National Semiconductor, which is helping with back end processes.

The work has started with attempts to make strontium titanate. "This has a permittivity of more than 100," said Prof O'Neill, "maybe 150." The next step is to integrate barium atoms into the compound to create an alloy system called barium strontium titanate. "This will allow us to tune various things in terms of performance."

Two approaches are being used to create the ultra thin ferroelectric films. While Newcastle is using ALD, Imperial is using pulsed laser deposition. Both approaches will allow deposition thicknesses with atomic level precision, but only ALD uses the low temperatures necessary for the integrated capacitors.

However, extensive characterisation will be needed to assess ferroelectric film quality. Alongside computer simulation, deposition and thermal parameters will be mapped to identify best ferroelectric properties for given constraints laid down by the silicon fabrication.

Once these tests have been concluded, transistors will be made incorporating the best ferroelectric films to confirm the reduction in sub threshold slope. By the end of the three and a half year project, the researchers hope that ferroelectric capacitors will have been integrated onto silicon.

Progress is being made. Prof O'Neill said 30, 40 and 50nm films have already been deposited using the ALD approach. "It's a useful approach," he noted, "because it provides a conformal coating. The film goes around everything, including transistors. If you want to make 3d structures, you get good coverage."

Materials are being assessed by making chip structures. "We'll then go on to look at mos transistors and capacitors incorporating ferroelectric films. But we need to see if we can make transistors"

Part of the work will be assessing the trade offs. "There are all sorts of issues along the way," Prof O'Neill pointed out. "You can create high permittivities, but there are trade offs. It's more likely that we will have to balance things in order to make a manufacturable product."

According to Prof O'Neill, thinner films might have higher capacitance, but might have more leakage. "There's a lot of engineering design to be undertaken and we are only a few months into the project."

Transistors will be made incorporating the best ferroelectric films to confirm the reduction in sub threshold slope. Ferroelectric capacitors integrated onto silicon will be demonstrated, allowing the capacitance increase per unit area to be quantified and the exploration of the fabrication constraints needed to maintain high transistor performance.

If the project proceeds according to plan, cmos devices of the future might be able to integrate a tuneable capacitor. "This will save silicon area and money," Prof O'Neill said. "But whether we get that far in the time we have for the FERN project remains to be seen. But we have excellent people in the project to take it forward."

Graham Pitcher is group editor at Findlay Media

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Graham Pitcher

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